CY8C24633
PSoC
®
Programmable System-on-Chip
Features
■
Powerful Harvard-architecture processor
❐
M8C processor speeds to 24 MHz
❐
8 × 8 multiply, 32-bit accumulate
❐
low Power at High Speed
❐
3.0 to 5.25 V operating voltage
❐
industrial temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC
®
Blocks)
❐
Four Rail-to-Rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 8-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
❐
Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• CRC and PRS modules
• Full-duplex UART
• Multiple SPI masters or slaves
• Connectable to all GPIO Pins
❐
Complex peripherals by combining blocks
❐
High speed 8-bit SAR ADC optimized for motor control
Precision, programmable clocking
❐
Internal ±5% 24/48 MHz oscillator
❐
High accuracy 24 MHz with optional 32 kHz crystal and PLL
❐
Optional external oscillator, up to 24 MHz
❐
Internal oscillator for watchdog and sleep
■
■
Flexible on-chip memory
❐
8K flash program storage 50,000 erase/write cycles
❐
256 bytes SRAM data storage
❐
In-System Serial Programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
EEPROM emulation in flash
Programmable pin configurations
❐
25 mA sink on all GPIO
❐
Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
❐
Up to eight Analog Inputs on GPIO plus two additional analog
inputs with restricted routing
❐
Two 30 mA analog outputs on GPIO
❐
Configurable interrupt on all GPIO
Additional system resources
2
❐
I C slave, master, and multi-master to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable low voltage detection
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
Complete development tools
❐
Free development Software (PSoC Designer™)
❐
Full-featured In-Circuit Emulator and programmer
❐
Full speed emulation
❐
Complex breakpoint structure
❐
128KB trace memory
■
■
■
■
Cypress Semiconductor Corporation
Document Number: 001-20160 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 19, 2012
CY8C24633
Block Diagram
Port 3
Port 2
Port 1 Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
Global Analog Interconnect
Flash 8K
Sleep and
Watchdog
SROM
CPUCore (M8C)
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
1 Row
4 Blocks
ANALOG SYSTEM
Analog
Block Array
2 Columns
4 Blocks
Analog
Ref
SAR8 ADC
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum.
Decimator
I
2
C
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Document Number: 001-20160 Rev. *G
Page 2 of 52
CY8C24633
Contents
Features ............................................................................. 1
Block Diagram .................................................................. 2
Contents ............................................................................ 3
PSoC Functional Overview .............................................. 4
The PSoC Core ........................................................... 4
The Digital System ...................................................... 4
The Analog System ..................................................... 5
Additional System Resources ..................................... 6
PSoC Device Characteristics ...................................... 6
Getting Started .................................................................. 7
Application Notes ........................................................ 7
Development Kits ........................................................ 7
Training ....................................................................... 7
CYPros Consultants .................................................... 7
Solutions Library .......................................................... 7
Technical Support ....................................................... 7
Development Tools .......................................................... 8
PSoC Designer Software Subsystems ........................ 8
Designing with PSoC Designer ....................................... 9
Select User Modules ................................................... 9
Configure User Modules .............................................. 9
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pinouts ............................................................................ 10
28-Pin Part Pinout ..................................................... 10
56-Pin Part Pinout ..................................................... 11
Register Reference ......................................................... 12
Register Conventions ................................................ 12
Register Mapping Tables .......................................... 12
Electrical Specifications ................................................ 15
Absolute Maximum Ratings ...................................... 16
Operating Temperature ............................................ 16
DC Electrical Characteristics ..................................... 17
AC Electrical Characteristics ..................................... 30
Thermal Impedances ................................................ 41
Capacitance on Crystal Pins .................................... 41
Solder Reflow Peak Temperature ............................. 41
Ordering Information ...................................................... 42
Packaging Information ................................................... 43
Acronyms ........................................................................ 44
Acronyms Used ......................................................... 44
Reference Documents .................................................... 44
Document Conventions ................................................. 45
Units of Measure ....................................................... 45
Numeric Conventions ................................................ 45
Glossary .......................................................................... 46
Document History Page ................................................. 51
Sales, Solutions, and Legal Information ...................... 52
Worldwide Sales and Design Support ....................... 52
Products .................................................................... 52
PSoC® Solutions ...................................................... 52
Document Number: 001-20160 Rev. *G
Page 3 of 52
CY8C24633
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chip with on-chip controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with one, low cost single-chip programmable
device. PSoC devices include configurable blocks of analog and
digital logic, as well as programmable interconnects. This
architecture allows the user to create customized peripheral
configurations that match the requirements of each individual
application. Additionally, a fast CPU, flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts and packages.
The PSoC architecture, as illustrated in the
Block Diagram,
is
comprised of four main areas: PSoC core, digital system, Analog
system, and system resources. Configurable global buses
allows all the device resources to be combined into a complete
custom system. The PSoC CY8C24x33 family can have up to
three I/O ports that connect to the global digital and analog
interconnects, providing access to four digital blocks and four
analog blocks.
The Digital System
The Digital System is composed of four digital PSoC blocks.
Each block is an 8-bit resource that can be used alone or
combined with other blocks to form 8-, 16-, 24-, and 32-bit
peripherals, which are called user module references.
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
Digital Clocks
FromCore
To System Bus
ToAnalog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Output
Configuration
The PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general purpose I/O (GPIO).
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard-architecture
microprocessor. The CPU utilizes an interrupt controller with 11
vectors, to simplify programming of real time embedded events.
Program execution is timed and protected using the included
sleep and watch dog timers (WDT).
Memory encompasses 8 KB of flash for program storage,
256 bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the flash. Program flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
±5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz internal low speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations include those listed below.
■
■
■
■
■
■
■
■
■
■
PWMs (8- and 16-bit)
PWMs with dead band (8- and 16-bit)
Counters (8- to 32-bit)
Timers (8- to 32-bit)
UART 8 bit with selectable parity (up to 1)
SPI master and slave (up to 1)
I
2
C slave and master (1 available as a system resource)
Cyclical redundancy checker/generator (8- to 32-bit)
IrDA (up to 1)
Pseudo random sequence generators (8- to 32-bit)
The digital blocks are connected to any GPIO through a series
of global buses that route any signal to any pin. The buses also
allow signal multiplexing and performing logic operations. This
configurability frees your designs from the constraints of a fixed
peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in
Table 1
on page 6.
Document Number: 001-20160 Rev. *G
Page 4 of 52
CY8C24633
The Analog System
The analog system is composed of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Each analog block is comprised of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific appli-
cation requirements. Some of the more common PSoC analog
functions (most available as user modules) are listed below.
■
■
■
■
■
■
■
■
■
■
■
■
■
Figure 2. Analog System Block Diagram
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[3]
P2[4]
P2[2]
P2[0]
Filters (2 and 4 pole band pass, low-pass, and notch)
Amplifiers (up to two, with selectable gain to 48x)
Instrumentation amplifiers (1 with selectable gain to 93x)
Comparators (up to two, with 16 selectable thresholds)
DACs (up to two, with 6- to 9-bit resolution)
Multiplying DACs (up to 2, with 6- to 9-bit resolution)
High current output drivers (two with 30 mA drive as a core
resource)
1.3 V reference (as a system resource)
P2[1]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
DTMF dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
ACB00
ACB01
ASD11
ASC21
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks. The analog column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
P0[7:0]
ACI2[3:0]
8-Bit SAR ADC
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-20160 Rev. *G
Page 5 of 52
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