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CY62137EV30_12

产品描述2-Mbit (128 K × 16) Static RAM
文件大小455KB,共18页
制造商Cypress(赛普拉斯)
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CY62137EV30_12概述

2-Mbit (128 K × 16) Static RAM

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CY62137EV30 MoBL
®
2-Mbit (128 K × 16) Static RAM
2-Mbit (128 K × 16) Static RAM
Features
Very high speed: 45 ns
Wide voltage range: 2.20 V to 3.60 V
Pin compatible with CY62137CV30
Ultra low standby power
Typical standby current: 1
A
Maximum standby current: 7
A
Ultra low active power
Typical active current: 2 mA at f = 1 MHz
Easy memory expansion with CE and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Byte power-down feature
Offered in Pb-free 48-ball very fine-pitch ball grid array
(VFBGA) and 44-pin thin small outline package (TSOP II)
package
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 90% when addresses are not toggling. The
device can also be put into standby mode reducing power
consumption when deselected (CE HIGH or both BLE and BHE
are HIGH). The input and output pins (I/O
0
through I/O
15
) are
placed in a high impedance state when: deselected (CE HIGH),
outputs are disabled (OE HIGH), both Byte High Enable and Byte
Low Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW and WE LOW).
Writing to the device is accomplished by asserting Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through
A
16
). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O
8
through I/O
15
) is written into the location specified on the
address pins (A
0
through A
16
).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appears on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW, then
data from memory appears on I/O
8
to I/O
15
. See the
Truth Table
on page 11
for a complete description of read and write modes.
The CY62137EV30 is available in 48-ball VFBGA and 44-pin
TSOPII packages.
Functional Description
The CY62137EV30 is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
128K x 16
RAM Array
SENSE AMPS
I/O
0
– I/O
7
I/O
8
– I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
BHE
BLE
A
13
A
14
A
15
A
16
A
12
Pow
-
er Down
Circuit
CE
A
11
Cypress Semiconductor Corporation
Document Number: 38-05443 Rev. *F
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised November 8, 2012

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