CY2DL15110
1:10 Differential LVDS Fanout Buffer
with Selectable Clock Input
1:10 Differential LVDS Fanout Buffer with Selectable Clock Input
Features
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Functional Description
The CY2DL15110 is an ultra-low noise, low skew, low
propagation delay 1:10 LVDS fanout buffer targeted to meet the
requirements of high speed clock distribution applications. The
CY2DL15110 can select between two separate differential
(LVPECL, LVDS, HCSL, or CML) input clock pairs using the
IN_SEL pin. The device has a fully differential internal
architecture that is optimized to achieve low additive jitter and
low skew at operating frequencies of up to 1.5 GHz.
For a complete list of related documentation,
click here.
Select one of two differential (LVPECL, LVDS, HCSL, or CML)
input pairs to distribute to 10 LVDS output pairs
Translate any single-ended input signal to 3.3 V LVDS level
with resistor bias on INx# input
40-ps maximum output-to-output skew
600-ps maximum propagation delay
0.11-ps maximum additive RMS phase jitter at 156.25 MHz
(12-kHz to 20-MHz offset)
Up to 1.5-GHz operation
32-pin thin quad flat pack (TQFP) package
2.5-V or 3.3-V operating voltage
[1]
Commercial and industrial operating temperature range
Logic Block Diagram
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-69398 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 13, 2017
CY2DL15110
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions ....................................................... 4
DC Electrical Specifications ............................................ 5
Thermal Resistance .......................................................... 5
AC Electrical Specifications ............................................ 6
Application Information ................................................... 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagram ............................................................ 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 14
Worldwide Sales and Design Support ....................... 14
Products .................................................................... 14
PSoC® Solutions ...................................................... 14
Cypress Developer Community ................................. 14
Technical Support ..................................................... 14
Document Number: 001-69398 Rev. *G
Page 2 of 14
CY2DL15110
Pinouts
Figure 1. Pin Diagram - CY2DL15110
Pin Definitions
Pin No.
1
2
Pin Name Pin Type
NC
IN_SEL
Input
No connection
Input clock select pin. Low-voltage complementary metal oxide semicon-
ductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL).
When IN_SEL = Low, the IN0/IN0# differential input pair is active
When IN_SEL = High, the IN1/IN1# differential input pair is active
Differential (LVPECL, HCSL, LVDS, or CML) input clock. Active when
IN_SEL = Low.
Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock.
Active when IN_SEL = Low.
LVDS reference voltage output
Differential (LVPECL, HCSL, LVDS, or CML) input clock. Active when
IN_SEL = High.
Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock.
Active when IN_SEL = High.
Do not Connect or Ground
Ground
LVDS complementary output clocks
LVDS output clocks
Power supply
Page 3 of 14
Description
3
4
5
6
7
8
9, 25
IN0
IN0#
V
BB
IN1
IN1#
NC/GND
V
SS
Input
Input
Output
Input
Input
NC
Power
Output
Output
Power
10, 12, 14, 17, 19, 21, 23, 26, 28, 30 Q(0:9)#
11, 13, 15, 18, 20, 22, 24, 27, 29, 31 Q(0:9)
16, 32
V
DD
Document Number: 001-69398 Rev. *G
CY2DL15110
Absolute Maximum Ratings
Parameter
V
DD
V
IN[2]
V
OUT[2]
T
S
ESD
HBM
L
U
UL–94
MSL
T
J
Supply voltage
Input voltage, relative to V
SS
DC output or I/O Voltage, relative to V
SS
Storage temperature
Electrostatic discharge (ESD) protection
(Human body model)
Latch up
Flammability rating
Moisture sensitivity level
Junction temperature
–
At 1/8 in.
Description
Condition
Nonfunctional
Nonfunctional
Nonfunctional
Nonfunctional
JEDEC STD 22-A114-B
Min
–0.5
–0.5
–0.5
–55
2000
Max
4.6
lesser of 4.0
or V
DD
+ 0.4
lesser of 4.0
or V
DD
+ 0.4
150
–
Unit
V
V
V
°C
V
Meets or exceeds JEDEC Spec
JESD78B IC latch up test
V–0
3
135
°C
Operating Conditions
Parameter
V
DD
T
A
t
PU
t
STARTUP
Supply voltage
Ambient operating temperature
Power ramp time
Description
Condition
2.5-V supply
3.3-V supply
Commercial
Industrial
Power-up time for V
DD
to reach
minimum supply voltage (power
ramp must be monotonic.)
Time taken from V
DD
reaching
95% of its minimum supply
voltage to the device being
operational.
Min
2.375
3.135
0
–40
0.05
Max
2.625
3.465
70
85
500
Unit
V
V
°C
°C
ms
Start up time
1
–
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required.
Document Number: 001-69398 Rev. *G
Page 4 of 14
CY2DL15110
DC Electrical Specifications
(V
DD
= 3.3 V ± 5% or 2.5 V ± 5%; T
A
= 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
I
DD
V
IH1
V
IL1
V
IH2
V
IL2
V
IH3
V
IL3
V
ID[5]
V
ICM
I
IH
I
IL
V
PP
V
OCM
V
BB
R
P
C
IN
Description
Operating supply current
Input high Voltage, LVDS input
clocks, IN0, IN0#, IN1, and IN1#
Input low voltage, LVDS input
clocks, IN0, IN0#, IN1, and IN1#
Input high voltage, IN_SEL
Input low voltage, IN_SEL
Input high voltage, IN_SEL
Input low voltage, IN_SEL
Input differential amplitude
Input common mode voltage
Input high current, All inputs
Input low current, All inputs
LVDS differential output voltage
peak to peak, single-ended
Change in V
OCM
between
complementary output states
Output reference voltage
Internal pull-up / pull-down
resistance, LVCMOS logic input
Input capacitance
V
DD
= 3.3 V
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 2.5 V
See
Figure 3 on page 7
See
Figure 3 on page 7
Input = V
DD[6]
Input = V
SS[6]
V
DD
= 3.3 V or 2.5 V,
R
TERM
= 100
between Q and Q# pairs
[3, 7]
V
DD
= 3.3 V or 2.5 V,
R
TERM
= 100
between Q and Q# pairs
[3, 7]
0 to 150
A
output current
IN_SEL pin has pull-down only
Measured at 10 MHz per pin
Condition
All LVDS outputs terminated with 100
load
[3, 4]
Min
–
–
–0.3
2.0
–0.3
1.7
–0.3
0.4
0.5
–
–150
250
–
1.125
60
–
Max
125
V
DD
+ 0.3
–
V
DD
+ 0.3
0.8
V
DD
+ 0.3
0.7
0.8
V
DD
– 0.2
150
–
470
50
1.375
140
3
Unit
mA
V
V
V
V
V
V
V
V
A
A
mV
mV
V
k
pF
Thermal Resistance
Parameter
[8]
θ
JA
θ
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
32-pin TQFP
69
14
Unit
°C/W
°C/W
Notes
3. Refer to
Figure 2 on page 7.
4. I
DD
includes current that is dissipated externally in the output termination resistors.
5. V
ID
minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with V
ID
minimum of greater than 200 mV.
6. Positive current flows into the input pin, negative current flows out of the input pin.
7. Refer to
Figure 4 on page 7.
8. These parameters are guaranteed by design and are not tested.
Document Number: 001-69398 Rev. *G
Page 5 of 14
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