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SX1257: 产品描述SPECIALTY TELECOM CIRCUIT; 产品类别热门应用无线/射频/通信; 文件大小1MB，共42页; 制造商SEMTECH; 官网地址http://www.semtech.com

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SX1257概述

SPECIALTY TELECOM CIRCUIT

专业电信电路

SX1257规格参数

参数名称	属性值
状态	ACTIVE
通信类型	TELECOM CIRCUIT

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SX1257

Low Power Digital I and Q RF

Multi-PHY Mode Transceiver

VBAT

VR_ANA1

VR_ANA2

VR_DIG

Power Distribution System

0 to -30 dB with 2 dB steps

0 to -48 dB with 6 dB steps

Single to Diff

RX pre-filter



I_OUT

RESET

RF_IN

RX pre-filter



Q_OUT

Div by 2

Fractional-N

Frequency Synthesizer

ATT

Control Registers and Interface

MISO

MOSI

SCK

NSS

CLKIN

CLKOUT

Div by 2

Fractional-N

Frequency Synthesizer

TX Filter

RF_OP

Driver

RF_ON

TX Filter

DAC

I_IN

DAC

Q_IN

36 MHz

XTA

XTB

Figure A: SX1257 Block Diagram

General Description

The SX1257 is a highly integrated RF front-end to digital I

and Q modulator/demodulator Multi-PHY mode

transceiver capable of supporting multiple constant and

non-constant envelope modulation schemes. It is designed

to operate over the 862 to 960 MHz European, North

American and Japanese ISM (Industrial, Scientific and

Medical) license-exempt frequency bands. Its highly

integrated architecture allows for a minimum of external

components whilst maintaining maximum design

flexibility. All major RF communication parameters are

programmable and most of them can be dynamically set.

The SX1257 offers support for both narrow-band and

wide-band communication modes without the need to

modify external components. The SX1257 is optimized for

low power consumption while offering the provision for

high RF output power and channelized operation. TrueRF™

technology enables a low-cost external component count

whilst still satisfying ETSI, FCC and ARIB regulations.

Applications

•

IEEE 802.15.4g SUN Multi-PHY Mode Smartgrid

Cognitive / Software Defined Radio (SDR)

Key Product Features

•

Fully flexible I and Q modulator and demodulator

Half or full-duplex operation

Bullet proof RX LNA

Analog TX and RX pre-filtering

Programmable tap TX FIR-DAC filter

Linear TX amplifier for both constant and non-constant

envelope modulation schemes

SX1257

Data Sheet

DS.SX1257.W.APP

www.semtech.com

Rev. 1.2

March 2018

1 of 42

Semtech

Table of Contents

1. General Description ........................................................................................................................................................................................ 7

1.1 Simplified Block Diagram ................................................................................................................................................................ 7

1.2 I/O Description .................................................................................................................................................................................... 8

1.3 Package View ....................................................................................................................................................................................... 9

2. Specifications ..................................................................................................................................................................................................10

2.1 ESD Notice ...........................................................................................................................................................................................10

2.2 Absolute Maximum Ratings .........................................................................................................................................................10

2.3 Operating Range ...............................................................................................................................................................................10

2.4 Electrical Specifications ..................................................................................................................................................................11

2.4.1 Power Consumption Specifications ..............................................................................................................................11

2.4.2 Frequency Synthesis Specifications ..............................................................................................................................11

2.4.3 Transmitter Front-End Specifications ...........................................................................................................................12

2.4.4 Receiver Front-End Specifications..................................................................................................................................13

2.4.5 SPI Bus Digital Specifications ...........................................................................................................................................14

3. Circuit Description.........................................................................................................................................................................................15

3.1 Power Supply Strategy ...................................................................................................................................................................15

3.2 Low Battery Detector ......................................................................................................................................................................15

3.3 Frequency Synthesizer ...................................................................................................................................................................15

3.3.1 Reference Oscillator.............................................................................................................................................................15

3.3.2 CLK_OUT Output ..................................................................................................................................................................16

3.3.3 PLL Architecture....................................................................................................................................................................16

3.4 Transmitter Analog Front-End Description .............................................................................................................................18

3.4.1 Architectural Description ..................................................................................................................................................18

3.4.2 TX I / Q Channel Filters .......................................................................................................................................................18

3.4.3 TX I / Q Up-Conversion Mixers.........................................................................................................................................20

3.4.4 RF Amplifier ............................................................................................................................................................................20

3.5 Transmitter Digital Baseband Description ..............................................................................................................................21

3.5.1 Digital-to-Analog Converters...........................................................................................................................................21

3.5.2 I and Q Serial Interface........................................................................................................................................................22

3.6 Receiver Analog Front-End Description ...................................................................................................................................23

3.6.1 Architectural Description ..................................................................................................................................................23

3.6.2 LNA and Single to Differential Buffer ............................................................................................................................23

3.6.3 I /Q Downconversion Quadrature Mixer......................................................................................................................23

3.6.4 Baseband Analog Filters and Amplifiers ......................................................................................................................24

3.7 Receiver Digital Baseband .............................................................................................................................................................24

3.7.1 Architectural Block Diagram ............................................................................................................................................24

3.7.2 Analog-to-Digital Converters...........................................................................................................................................24

3.7.3 Temperature Sensor............................................................................................................................................................25

3.7.4 I and Q Serial Interface........................................................................................................................................................25

3.8 Loop-Back ............................................................................................................................................................................................26

3.8.1 Digital Loop-Back .................................................................................................................................................................26

3.8.2 RF Loop Back..........................................................................................................................................................................26

4. Digital Interface..............................................................................................................................................................................................27

SX1257

Data Sheet

DS.SX1257.W.APP

www.semtech.com

Rev. 1.2

March 2018

3 of 42

Semtech

4.1 SPI Bus Interface ................................................................................................................................................................................27

4.2 Digital IO Pin Mapping ...................................................................................................................................................................28

5. Configuration and Status Registers .......................................................................................................................................................29

5.1 General Description .........................................................................................................................................................................29

5.2 Mode Configuration Registers .....................................................................................................................................................30

5.3 Frequency Synthesizer Configuration Registers ...................................................................................................................31

5.4 Transmitter Front-End Configuration Registers ....................................................................................................................32

5.5 Receiver Front-End Configuration Registers ..........................................................................................................................33

5.6 DIO Mapping Configuration Registers ......................................................................................................................................34

5.7 Additional Parameter Configuration Registers ......................................................................................................................34

6. Application Information.............................................................................................................................................................................36

6.1 Crystal Resonator Specification ...................................................................................................................................................36

6.2 Reset of the Chip ...............................................................................................................................................................................36

6.2.1 POR ............................................................................................................................................................................................36

6.2.2 Manual Reset..........................................................................................................................................................................37

6.2.3 TX Noise Shaper ....................................................................................................................................................................37

6.3 Application Schematics ..................................................................................................................................................................38

7. Packaging Information ................................................................................................................................................................................39

7.1 Package Outline Drawing ..............................................................................................................................................................39

7.2 Recommended Land Pattern .......................................................................................................................................................40

7.3 Package Marking ..............................................................................................................................................................................40

7.4 Thermal Impedance .........................................................................................................................................................................41

7.5 Tape and Reel Specification ..........................................................................................................................................................41

SX1257

Data Sheet

DS.SX1257.W.APP

www.semtech.com

Rev. 1.2

March 2018

4 of 42

Semtech

List of Figures

Figure 1-1: SX1257 Block Diagram................................................................................................................................................................ 7

Figure 1-2: SX1257 Top View Pin Location................................................................................................................................................. 9

Figure 3-1: TCXO Connection ....................................................................................................................................................................... 16

Figure 3-2: SX1257 Transmitter Analog Front-End Block Diagram................................................................................................. 18

Figure 3-3: FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 32 ............................................................. 21

Figure 3-4: FIR-DAC Normalized Magnitude Response with fS = 32 MHz and N = 64 ............................................................. 22

Figure 3-5: Transmitter I and Q Channel Bit-Stream Timing Diagram ........................................................................................... 22

Figure 3-6: SX1257 Receiver Analog Front-End Block Diagram ....................................................................................................... 23

Figure 3-7: SX1257 Digital Receiver Baseband Block Diagram......................................................................................................... 24

Figure 3-8: Temperature Sensor Response.............................................................................................................................................. 25

Figure 3-9: Receiver I and Q Channel Bit-Stream Timing Diagram ................................................................................................. 25

Figure 3-10: Digital and RF Loop-Back Paths .......................................................................................................................................... 26

Figure 4-1: SPI Timing Diagram (Single Access)..................................................................................................................................... 27

Figure 6-1: POR Timing Diagram ................................................................................................................................................................. 36

Figure 6-2: Manual Reset Timing Diagram............................................................................................................................................... 37

Figure 6-3: Example of a Digital Modulator Implementation ........................................................................................................... 37

Figure 6-4: Application Schematic of the SX1257 ................................................................................................................................. 38

Figure 7-1: Package Outline Drawing ........................................................................................................................................................ 39

Figure 7-2: Recommended Land Pattern ................................................................................................................................................. 40

Figure 7-3: SX1257 Marking Diagram ........................................................................................................................................................ 40

Figure 7-4: Tape and Reel Specification.................................................................................................................................................... 41

SX1257

Data Sheet

DS.SX1257.W.APP

www.semtech.com

Rev. 1.2

March 2018

5 of 42

Semtech

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