NT1GD64S8HA0F
1GB : 128M x 64
PC2700 / PC2100 Unbuffered DDR DIMM
184-pin Unbuffered DDR DIMM
Based on DDR333/266 64Mx8 SDRAM
Features
• 128Mx64 Unbuffered DDR DIMM based on 64Mx8 DDR
SDRAM
• 184-pin Dual In-Line Memory Module
• Performance:
PC2700 PC2100
Speed Sort
DIMM
CAS
Latency
f
CK
t
CK
Clock Frequency
Clock Cycle
6K
2.5
166
6
333
75B
2.5
133
7.5
266
MHz
ns
MHz
Unit
• DRAM DLL aligns DQ and DQS transitions with clock transitions
• Address and control signals are fully synchronous to positive
clock edge
• Programmable Operation:
- DIMM
CAS
Latency: 2, 2.5
- Burst Type: Sequential or Interleave
- Burst Length: 2, 4, 8
- Operation: Burst Read and Write
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 13/11/2 Addressing (row/column/bank)
• 7.8
µs
Max. Average Periodic Refresh Interval
• Serial Presence Detect
• Gold contacts
• SDRAMs in 60-ball FBGA Package
f
DQ
DQ Burst Frequency
• Intended for 133 MHz and 166 MHz applications
• Inputs and outputs are SSTL-2 compatible
• V
DD
= 2.5Volt ± 0.2, V
DDQ
= 2.5V ± 0.2V
• SDRAMs have 4 internal banks for concurrent operation
• Differential clock inputs
• Data is read or written on both clock edges
Description
NT1GD64S8HA0F is an unbuffered 184-Pin Double Data Rate (DDR) Synchronous DRAM Dual In-Line Memory Module (DIMM),
organized as a two-bank 128Mx64 high-speed memory array. The module uses four 64Mx8 DDR SDRAMs in 60-ball FBGA packages.
All NANYA DDR SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 166 MHz clock speeds and achieves high-speed data transfer rates of up to
333 MHz. Prior to any access operation, the device
CAS
latency and burst type/ length/operation type must be programmed into the
DIMM by address inputs A0-A12 and I/O inputs BA0 and BA1 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
Ordering Information
Part Number
NT1GD64S8HA0F-6K
Speed
166MHz (6ns @ CL = 2.5)
133MHz (7.5ns @ CL = 2)
133MHz (7.5ns @ CL = 2.5)
100MHz (10ns @ CL = 2)
DDR333
PC2700
128Mx64
DDR266B
PC2100
Gold
2.5V
Organization
Leads
Power
NT1GD64S8HA0F-75B
REV 0.2
12/2003
1
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GD64S8HA0F
1GB : 128M x 64
PC2700 / PC2100 Unbuffered DDR DIMM
Pin Description
CK0, CK1, CK2,
Differential Clock Inputs
CK0, CK1, CK2
CKE0, CKE1
RAS
CAS
WE
S0, S1
A10/AP
BA0, BA1
V
REF
V
DDID
Clock Enable
Row Address Strobe
Column Address Strobe
Write Enable
Chip Selects
Address Input/Auto precharge
SDRAM Bank Address Inputs
Ref. Voltage for SSTL_2 inputs
V
DD
Identification flag
(Not used when V
DD
= V
DDQ
)
DQ0-DQ63
DQS0-DQS7
DM0-DM7
V
DD
V
DDQ
V
SS
NC
SCL
SDA
SA0-2
V
DDSPD
Data input/output
Bi-directional data strobes
Input Data Mask
Power (2.5V)
Supply voltage for DQs (2.5V)
Ground
No Connect
Serial Presence Detect Clock Input
Serial Presence Detect Data input/output
Serial Presence Detect Address Inputs
Serial EEPROM positive power supply (2.5V)
A0-A9, A11, A12 Address Inputs
Pinout
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Front
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DDQ
CK1
CK1
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DDQ
DQ19
Pin
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
Back
V
SS
DQ4
DQ5
V
DDQ
DM0/DQS9
DQ6
DQ7
V
SS
NC
NC
NC
V
DDQ
DQ12
DQ13
DM1/DQS10
V
DD
DQ14
DQ15
CKE1
V
DDQ
NC
DQ20
A12
V
SS
DQ21
A11
DM2/DQS11
V
DD
DQ22
A8
DQ23
53
54
55
56
57
58
59
60
61
Pin
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
KEY
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
Front
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
NC
NC
V
DD
NC
A0
NC
V
SS
NC
BA1
Pin
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Back
V
SS
A6
DQ28
DQ29
V
DDQ
DM3/DQS12
A3
DQ30
V
SS
DQ31
NC
NC
V
DDQ
CK0
CK0
V
SS
NC
A10
NC
V
DDQ
NC
KEY
V
SS
DQ36
DQ37
V
DD
DM4/DQS13
DQ38
DQ39
V
SS
DQ44
Pin
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Front
V
DDQ
WE
DQ41
CAS
V
SS
DQS5
DQ42
DQ43
V
DD
NC
DQ48
DQ49
V
SS
CK2
CK2
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
WP
SDA
SCL
Pin
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Back
RAS
DQ45
V
DDQ
S0
S1
DM5/DQS14
V
SS
DQ46
DQ47
NC
V
DDQ
DQ52
DQ53
NC
V
DD
DM6/DQS15
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DM7/DQS16
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DDSPD
Note: All pin assignments are consistent for all 8-byte unbuffered versions.
REV 0.2
12/2003
2
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GD64S8HA0F
1GB : 128M x 64
PC2700 / PC2100 Unbuffered DDR DIMM
Input/Output Functional Description
Symbol
CK0, CK1, CK2
CK0, CK1, CK2
CKE0, CKE1
Type
(SSTL)
(SSTL)
(SSTL)
Polarity
Function
Positive The positive line of the differential pair of system clock inputs. All the DDR SDRAM
Edge address and control inputs are sampled on the rising edge of their associated clocks.
Negative
The negative line of the differential pair of system clock inputs.
Edge
Active
High
Active
Low
Active
Low
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self-Refresh
mode.
Enables the associated SDRAM command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new commands are ignored
but previous operations continue.
When sampled at the positive rising edge of the clock,
RAS, CAS, WE
define the operation
to be executed by the SDRAM.
Reference voltage for SSTL-2 inputs
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Auto-precharge operation at the end of the Burst Read or Write cycle. If AP is high,
auto-precharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
auto-precharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
Data and Check Bit input/output pins operate in the same manner as on conventional
DRAMs.
Data strobes: Output with read data, input with write data. Edge aligned with read data,
centered on write data. Used to capture write data.
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if it
is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
Power and ground for the DDR SDRAM input buffers and core logic
-
-
-
Supply
Address inputs. Connected to either V
DD
or V
SS
on the system board to configure the
Serial Presence Detect EEPROM address.
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V
DD
to act as a pull-up.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V
DD
to act as a pull-up.
Serial EEPROM positive power supply.
S0, S1
RAS, CAS, WE
V
REF
V
DDQ
BA0, BA1
(SSTL)
(SSTL)
Supply
Supply
(SSTL)
A0 - A9
A10/AP
A11, A12
(SSTL)
-
DQ0 - DQ63
DQS0 - DQS7
(SSTL)
(SSTL)
-
Active
High
Active
High
DM0 - DM7
V
DD
,
V
SS
SA0 - SA2
SDA
SCL
V
DDSPD
Input
Supply
REV 0.2
12/2003
3
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GD64S8HA0F
1GB : 128M x 64
PC2700 / PC2100 Unbuffered DDR DIMM
Functional Block Diagram
(2 Banks, 64Mx8 DDR SDRAMs)
S1
S0
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS7
DM7/DQS16
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6
DM6/DQS15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS5
DM5/DQS14
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
DQS4
DM4/DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
DM
I/O 0
I/O 1
I/O 6
I/O 7
I/O 2
I/O 3
I/O 4
I/O 5
CS
DQS
D0
D8
D4
D12
D1
D9
D5
D13
D2
D10
D6
D14
D3
D11
D7
D15
BA0-BA1
A0-A12
RAS
CAS
CKE0
CKE1
WE
Notes :
1.
2.
3.
4.
BA0-BA1 : SDRAMs D0-D15
A0-A12 : SDRAMs D0-D15
RAS
: SDRAMs D0-D15
CAS
: SDRAMs D0-D15
CKE : SDRAMs D0-D7
CKE : SDRAMs D8-D15
WE
: SDRAMs D0-D15
V
DDSPD
V
DD
/V
DDQ
V
REF
V
SS
V
DDID
Serial PD
SCL
WP
A0
SA0
A1
SA1
SPD
D0-D15
D0-D15
D0-D15
Strap: see Note 4
* Clock Wiring
Clock Input
SDRAMs
*CK0/CK0
4 SDRAMs
*CK1/CK1
6 SDRAMs
*CK2/CK2
6 SDRAMs
* Wire per Clock Loading Table/
Wiring Diagrams
A2
SA2
SDA
* Clock Net Wiring
R=120 Ohms
D3/D0/D5
D11/D8/D13
Cap/D1/D6
Cap/D9/D14
D4/D2/D7
D12/D10/D15
DQ-to-I/O wiring is shown as recommended but may be changed.
DQ/DQS/DM/CKE/S relationships must be maintained as shown.
DQ, DQS, DM/DQS resistors: 22 Ohms.
V
DDID
strap connections (for memory device V
DD
, V
DDQ
):
STRAP OUT (OPEN): V
DD
= V
DDQ
STRAP IN (V
SS
): V
DD
is not equal to V
DDQ
.
CK0/CK1/CK2
CK0/CK1/CK2
Card
Edge
REV 0.2
12/2003
4
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
NT1GD64S8HA0F
1GB : 128M x 64
PC2700 / PC2100 Unbuffered DDR DIMM
Serial Presence Detect --
Part 1 of 2
128Mx64 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 2.5V DDR SDRAMs with SPD
SPD Entry Value
Byte
Description
DDR333
-6K
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36-40
41
42
43
44
45
46-61
62
63
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Bank
Data Width of Assembly
Data Width of Assembly (cont’)
Voltage Interface Level of this Assembly
DDR SDRAM Device Cycle Time at CL=2.5
DDR SDRAM Device Access Time from Clock at CL=2.5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR SDRAM Width
Error Checking DDR SDRAM Device Width
DDR SDRAM Device Attr: Min CLK Delay, Random Col
Access
DDR SDRAM Device Attributes: Burst Length Supported
DDR SDRAM Device Attributes: Number of Device Banks
DDR SDRAM Device Attributes: CAS Latencies Supported
DDR SDRAM Device Attributes: CS Latency
DDR SDRAM Device Attributes: WE Latency
DDR SDRAM Device Attributes:
DDR SDRAM Device Attributes: General
Minimum Clock Cycle at CL=2
Maximum Data Access Time from Clock at CL=2
Minimum Clock Cycle Time at CL=1
Maximum Data Access Time from Clock at CL=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active delay (t
RRD
)
Minimum RAS to CAS delay (t
RCD
)
Minimum RAS Pulse Width (t
RAS
)
Module Bank Density
Address and Command Setup Time Before Clock
Address and Command Hold Time After Clock
Data Input Setup Time Before Clock
Data Input Hold Time After Clock
Reserved
Minimum Active/Auto-refresh Time (t
RC
)
Auto-refresh to Active/Auto-refresh Command Period (t
RFC
)
Max Cycle Time (t
CK max
)
Maximum DQS-DQ Skew Time (t
DQSQ
)
Maximum Read Data Hold Skew Factor (t
QHS
)
Reserved
SPD Revision
Checksum Data
0.75ns
0.75ns
0.45ns
0.45ns
0
60ns
72ns
12ns
0.4ns
0.55ns
0
Initial
4C
18ns
12ns
18ns
42ns
512MB
0.9ns
0.9ns
0.5ns
0.5ns
75
75
45
45
00
3C
48
30
28
55
00
00
01
2/2.5
0
1
Differential Clock
+/-0.2V Voltage Tolerance
7.5ns
0.70ns
N/A
N/A
20ns
15ns
20ns
45ns
48
30
48
2A
80
90
90
50
50
10ns
0.75ns
75
70
00
00
50
3C
50
2D
6ns
0.7ns
128
256
SDRAM DDR
13
11
2
X64
X64
SSTL 2.5V
7.5ns
0.75ns
Non-Parity
SR/1x(7.8us)
X8
N/A
1 Clock
2,4,8
4
2/2.5
0C
01
02
20
00
A0
75
60
70
00
82
08
00
01
0E
04
0C
DDR266B
-75B
Serial PD Data Entry
(Hexadecimal)
DDR333
-6K
80
08
07
0D
0B
02
40
00
04
75
75
DDR266B
-75B
Note
REV 0.2
12/2003
5
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
© NANYA TECHNOLOGY CORP.
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