DA6181B.002
5 May, 2011
MAS6181B
AM Receiver IC
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DESCRIPTION
The MAS6181 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to
receive time signals in the frequency range from 40
kHz to 100 kHz. Only a few external components are
required for time signal receiving. The circuit has
preamplifier, wide range automatic gain control,
demodulator and output comparator built in. The
output signal can be processed directly by an
additional digital circuitry to extract the data from the
received signal. The control for AGC (automatic gain
control) can be used to switch AGC on or off if
necessary.
The MAS6181 supports receiving two different
frequency signals by two selective crystal filters and
an integrated switch to switch between two antenna
frequencies. It has differential input for improved
common mode disturbance rejection.
Dual Band Receiver IC
High Sensitivity
Very Low Power Consumption
Wide Supply Voltage Range
Power Down Control
Control for AGC On
High Selectivity by Crystal Filter
Fast Startup Feature
FEATURES
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Dual Band Receiver IC
Highly Sensitive AM Receiver
Wide Supply Voltage Range from 1.1 V to 3.6 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
Differential Input
APPLICATIONS
•
Multi Band Time Signal Receiver WWVB (USA),
JJY (Japan), DCF77 (Germany), MSF (UK), HBG
(Switzerland) and BPC (China)
BLOCK DIAGRAM
VDD
QO2 QO1
QI
AON
Demodulator
&
Comparator
OUT
RFIP
VDD
AGC Amplifier
RFIM
RFI2
Power Supply/Biasing
VDD
VSS PDN1 PDN2
AGC
DEC
1 (15)
DA6181B.002
5 May, 2011
PAD LAYOUT
MAS6181B1
1st bond!
VDD
RFIMB
RFI2B
VSS
RFI2
1530
µ
m
RFIM
RFIP
Do not bond!
PDN1
AON
DEC
QO2
QO1
QI
AGC
PDN2
OUT
1120
µ
m
DIE size = 1120 x 1530
µm;
rectangular PAD 80
µm
x 80
µm
Note:
Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left
floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note:
Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Power Supply Voltage
Quartz Filter Output for Crystal 2
Quartz Filter Output for Crystal 1
Quartz Filter Input for Crystals
AGC Capacitor
Power Down/Frequency Selection Input 2
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down/Frequency Selection Input 1
Positive Receiver Input
Negative Receiver Input
Test pad RFIMB
Test pad RFI2B
Receiver Input 2 (for Antenna Capacitor 2)
Power Supply Ground
Name
VDD
QO2
QO1
QI
AGC
PDN2
OUT
DEC
AON
PDN1
RFIP
RFIM
RFIMB
RFI2B
RFI2
VSS
X-coordinate
126
µm
126
µm
126
µm
126
µm
126
µm
126
µm
126
µm
994
µm
994
µm
994
µm
994
µm
994
µm
298
µm
400
µm
994
µm
994
µm
Y-coordinate
1332
µm
1132
µm
962
µm
788
µm
614
µm
440
µm
263
µm
266
µm
450
µm
618
µm
807
µm
985
µm
1025
µm
1025
µm
1163
µm
1321
µm
Note
1
2
3
1
4
4
5
5
Notes:
1) PDN1 = VDD and PDN2 = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down controlled to power on
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced
(modulated)
-
The output is a current source/sink with |I
OUT
| > 5
µA
-
At power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation)
-
Unused AON pad can be left unconnected due to internal pull-up with current < 1
µA.
Pull up current is
switched off at power down.
4) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD
5) RFIMB and RFI2B pads are left unconnected. They are only for wafer level testing purposes
2 (15)
DA6181B.002
5 May, 2011
ABSOLUTE MAXIMUM RATINGS
Parameter
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Symbol
V
DD
-V
SS
V
IN
T
OP
T
ST
Conditions
Min
-0.3
V
SS
-0.3
-40
-55
Max
3.6
V
DD
+0.3
+85
+150
Unit
V
V
o
C
o
C
Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will
not be destroyed.
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.5V, Temperature = 27°C unless otherwise noted
Parameter
Operating Voltage
Current Consumption
Symbol
V
DD
I
DD
Conditions
VDD=1.5 V, Vin=0
µVrms
VDD=1.5 V, Vin=20 mVrms
VDD=3.6 V, Vin=0
µVrms
VDD=3.6 V, Vin=20 mVrms
Min
1.10
Typ
1.5
66
40
68
42
Max
3.6
Unit
V
µA
31
24
40
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Receiver Input Resistance
Receiver Input Capacitance
RFI2 Switch On Resistance
RFI2 Switch Off Capacitance
Input Levels |l
IN
|<0.5
µA
Output Current
V
OL
<0.2 V
DD
;V
OH
>0.8 V
DD
DCF77 Output Pulses
MSF Output Pulses
I
DDoff
f
IN
V
IN min
V
IN max
R
RFI
C
RFI
R
ON2
C
OFF2
V
IL
V
IH
|I
OUT
|
T
100ms
T
200ms
T
100ms
T
200ms
T
300ms
T
500ms
T
200ms
T
500ms
T
800ms
T
200ms
T
500ms
T
800ms
T
200ms
T
500ms
T
800ms
T
Start
T
Delay
0.4
20
f=40kHz...77.5 kHz
VDD=1.4 V
600
1.1
5
20
V
DD
-0.35
5
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
95
195
120
220
320
520
200
500
800
210
505
800
200
495
790
1.3
3.5
50
85
65
0.1
100
1
µA
kHz
µVrms
mVrms
kΩ
pF
Ω
pF
V
µA
ms
ms
15
0.35
WWVB Output Pulses
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
Fast Start-up, Vin=0.4
µVrms
Fast Start-up, Vin=20 mVrms
ms
JJY60 Output Pulses
ms
JJY40 Output Pulses
ms
Startup Time
Output Delay Time
s
100
ms
Note:
Stand-by current consumption may increase if V
IH
and V
IL
differ from VDD and GND respectively.
Note:
See Note 6: Time Signal Software’s Pulse Width Recognition Limits and Table 5 on page 9!
3 (15)
DA6181B.002
5 May, 2011
FREQUENCY SELECTION
The power down control and frequency selection
using internal antenna’s tuning capacitor switch
(RFI2) are achieved by two digital control pins
Table 1.
Frequency selection and power down control
PDN1
PDN2
RFI2 Switch
High
High
Low
Low
High
Low
High
Low
Open
Open
Closed
Closed
PDN1 and PDN2. The control logic is presented in
table 1.
Description
Power down
Antenna frequency 1
Antenna frequency 2, RFI2 capacitor connected in parallel with antenna
Antenna frequency 2, RFI2 capacitor connected in parallel with antenna
the lowest
frequencies.
frequency
of
the
two
selected
If frequency 1 is selected the RFI2 switch is open
(non conductive). Antenna frequency is determined
by antenna inductor L
ANT
(see Typical Application on
page 5), antenna capacitor C
ANT1
and parasitic
capacitances related to antenna coil, inputs RFIP,
RFIM
and
RFI2
(see
Antenna
Tuning
Considerations below). Frequency 1 is the highest
frequency of the two selected frequencies.
If frequency 2 is selected then RFI2 switch is closed
to connect C
ANT2
to pin RFIM in parallel with ferrite
antenna and tune it to frequency 2. Frequency 2 is
It is recommended to switch the device to power
down for at least 50ms before switching to another
frequency. This guarantees fast startup in switching
to another frequency. During minimum 50ms power
down time the AGC capacitor voltage is completely
pulled to VDD to initialize proper startup conditions
for the AGC. Without the described proper fast
startup control the startup time can be several
minutes. With fast startup it is shortened typically to
a few seconds.
ANTENNA TUNING CONSIDERATIONS
The ferrite bar antenna having inductance L
ANT
and
parasitic coil capacitance C
COIL
is tuned to two
reception frequencies f
1
and f
2
by parallel capacitors
C
ANT1
and C
ANT2
. The receiver input stage and
internal
antenna
capacitor
switches
have
capacitances C
RFI
and C
OFF2
which affect the
Frequency f
1
(highest frequency):
C
TOT1
~C
COIL
+C
ANT1
+C
RFI
+C
OFF2
, assuming C
ANT2
>>C
OFF2
1
f
1
=
2
π
L
ANT
⋅
C
TOT
1
Frequency f
2
(lowest frequency):
C
TOT2
=C
COIL
+C
ANT1
+C
ANT2
+C
RFI
1
f
2
=
2
π
L
ANT
⋅
C
TOT
2
resonance frequencies. C
OFF2
is switch capacitance
when switch is open. When the antenna switch is
closed the off capacitance is shorted by on
resistance of the switch and it is effectively
eliminated. Following relationships can be written
for the two tuning frequencies.
4 (15)
DA6181B.002
5 May, 2011
TYPICAL APPLICATION
Note 1
X
2
X
1
Note 4
Optional
Control
for AGC on/hold
QI
AON
Demodulator
&
Comparator
OUT
Receiver
Output
Note 5
RFIP
VDD
QO2 QO1
L
ANT
C
ANT1
C
ANT2
VDD
AGC Amplifier
Ferrite
Antenna
RFIM
RFI2
Power Supply/Biasing
VDD
V
BATTERY
VSS PDN1 PDN2
AGC
C
AGC
10
µ
F
Power Down /
VDD
VDD
Note 3
Fast Startup /
Note 2
Frequency Selection
DEC
C
DEC
47 nF
Figure 1.
Application circuit of dual band receiver MAS6181
X
2
40003 Hz
X
1
60003 Hz
Note 1
Note 4
Optional
Control
for AGC on/hold
QI
AON
Demodulator
&
Comparator
OUT
Receiver
Output
Note 5
L
ANT
3.64 mH
C
ANT1
2.4 nF
RFIP
VDD
QO2 QO1
C
ANT1
1.9 nF
VDD
AGC Amplifier
Ferrite
Antenna
RFIM
RFI2
Power Supply/Biasing
VDD
V
BATTERY
VSS PDN1 PDN2
AGC
C
AGC
10
µ
F
Power Down /
VDD
VDD
Note 3
Fast Startup /
Note 2
Frequency Selection
DEC
C
DEC
47 nF
Figure 2.
Example circuit of dual band receiver MAS6181 for JJY 60 kHz and 40 kHz frequencies
5 (15)
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