DA6180B.002
5 May, 2011
MAS6180B
AM Receiver IC
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DESCRIPTION
The MAS6180 AM-Receiver chip is a highly sensitive,
simple to use AM receiver specially intended to receive
time signals in the frequency range from 40 kHz to 100
kHz. Only a few external components are required for
time signal receiver. The circuit has preamplifier, wide
range automatic gain control, demodulator and output
comparator built in. The output signal can be
processed directly by an additional digital circuitry to
extract the data from the received signal. The control
for AGC (automatic gain control) can be used to switch
AGC on or off if necessary.
MAS6180 has two options for compensating shunt
capacitances of different crystals (See ordering
information on page 14).
Single Band Receiver IC
High Sensitivity
Very Low Power Consumption
Wide Supply Voltage Range
Power Down Control
Control for AGC On
High Selectivity by Crystal Filter
Fast Startup Feature
FEATURES
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Single Band Receiver IC
Highly Sensitive AM Receiver
Wide Supply Voltage Range from 1.1 V to 3.6 V
Very Low Power Consumption
Power Down Control
Fast Startup
Only a Few External Components Necessary
Control for AGC On
Wide Frequency Range from 40 kHz to 100 kHz
High Selectivity by Quartz Crystal Filter
Crystal Compensation Capacitance Options
Differential Input
APPLICATIONS
•
Single Band Time Signal Receiver WWVB (USA),
JJY (Japan), DCF77 (Germany), MSF (UK), HBG
(Switzerland) and BPC (China)
BLOCK DIAGRAM
VDD
QOP
QI
QOM
AON
Demodulator
&
Comparator
OUT
RFIP
VDD
AGC Amplifier
RFIM
Power Supply/Biasing
VDD
VSS
PDN
AGC
DEC
1 (14)
DA6180B.002
5 May, 2011
MAS6180 PAD LAYOUT
VSS pad
bonded first!
1020
µ
m
VDD
QOP
QOM
QI
AGC
OUT
MAS6180Bx
VSS
RFIM
1260
µ
m
Y-coordinate
1062
µm
893
µm
723
µm
549
µm
375
µm
198
µm
201
µm
385
µm
553
µm
742
µm
920
µm
1051
µm
RFIP
PDN
AON
DEC
DIE size = 1020
µm
x 1260
µm;
PAD size = 80
µm
x 80
µm
Note:
Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left
floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly
are recommended to be performed in ESD protected area.
Note:
Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die.
Pad Identification
Power Supply Voltage
Positive Quartz Filter Output for Crystal
Negative Quartz Filter Output for Crystal
Quartz Filter Input for Crystal and External
Compensation Capacitor
AGC Capacitor
Receiver Output
Demodulator Capacitor
AGC On Control
Power Down
Positive Receiver Input
Negative Receiver Input
Power Supply Ground
Name
VDD
QOP
QOM
QI
AGC
OUT
DEC
AON
PDN
RFIP
RFIM
VSS
X-coordinate
126
µm
126
µm
126
µm
126
µm
126
µm
126
µm
894
µm
894
µm
894
µm
894
µm
894
µm
894
µm
Note
1
2
3
4
5
5
Notes:
1) External crystal compensation capacitor pin QOM is connected only in MAS6180B5 version. It is left
unconnected in MAS6180B1 version which has internal compensation capacitor.
2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated)
-
The output is a current source/sink with |I
OUT
| > 5
µA
-
At power down the output is pulled to VSS (pull down switch)
3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation)
-
Unused AON pad can be left unconnected due to internal pull-up with current < 1
µA.
Pull up current is
switched off at power down.
4) PDN = VSS means receiver on; PDN = VDD means receiver off
-
Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up
(PDN=VSS) i.e. at the falling edge of PDN signal.
5) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD
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DA6180B.002
5 May, 2011
6)
ABSOLUTE MAXIMUM RATINGS
All Voltages with Respect to Ground
Parameter
Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
Symbol
V
DD
-V
SS
V
IN
T
OP
T
ST
Conditions
Min
- 0.3
V
SS
-0.3
-40
- 55
Max
3.6
V
DD
+0.3
+85
+150
Unit
V
V
°
C
°
C
Note:
Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it
will not be destroyed.
Note:
This is a CMOS device and therefore it should be handled carefully to avoid any damage by static voltages (ESD).
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.5V, Temperature = 27° unless otherwise specified.
C,
Parameter
Operating Voltage
Current Consumption
Symbol
V
DD
I
DD
Conditions
VDD=1.5 V, Vin=0
µVrms
VDD=1.5 V, Vin=20 mVrms
VDD=3.6 V, Vin=0
µVrms
VDD=3.6 V, Vin=20 mVrms
See note below.
Min
1.1
Typ
1.5
66
40
68
42
Max
3.6
Unit
V
µA
31
24
40
Stand-By Current
Input Frequency Range
Minimum Input Voltage
Maximum Input Voltage
Receiver Input Resistance
Receiver Input Capacitance
Input Levels |l
IN
|<0.5
µA
Output Current
V
OL
<0.2 V
DD
;V
OH
>0.8 V
DD
DCF77 Output Pulses
MSF Output Pulses
I
DDoff
f
IN
V
IN min
V
IN max
R
RFI
C
RFI
V
IL
V
IH
|I
OUT
|
T
100ms
T
200ms
T
100ms
T
200ms
T
300ms
T
500ms
T
200ms
T
500ms
T
800ms
T
200ms
T
500ms
T
800ms
T
200ms
T
500ms
T
800ms
T
Start
T
Delay
0.4
20
Differential Input,
f=40 kHz…77.5 kHz
V
DD
-0.35
5
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
95
195
120
220
320
520
200
500
800
210
505
800
200
495
790
1.3
3.5
50
600
1.1
85
65
0.1
100
1
µA
kHz
µVrms
mVrms
kΩ
pF
V
µA
ms
ms
0.35
WWVB Output Pulses
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
1
µVrms ≤
V
IN
≤
20 mVrms, see note below!
Fast Start-up, Vin=0.4
µVrms
Fast Start-up, Vin=20 mVrms
ms
JJY60 Output Pulses
ms
JJY40 Output Pulses
ms
Startup Time
Output Delay Time
s
100
ms
Note:
Stand-by current consumption may increase if V
IH
and V
IL
differ from VDD and 0 respectively.
Note:
See Note 6: Time Signal Software’s Pulse Width Recognition Limits and Table 5 on page 8!
3 (14)
DA6180B.002
5 May, 2011
TYPICAL APPLICATION
Note 1
MAS6180B1
VDD
Note 4
Optional
Control
for AGC on/hold
QI
QOM
AON
Demodulator
&
Comparator
OUT
Receiver
Output
Note 5
RFIP
Ferrite
Antenna
VDD
QOP
AGC Amplifier
RFIM
VDD
Power Supply/Biasing
VDD
VSS
PDN
AGC
C
AGC
10
µ
F
VDD
DEC
C
DEC
47 nF
VDD
VDD
1.4 V
GND
Note 3
Power Down /
Fast Startup
Control
Note 2
Figure 1.
Application circuit of internal compensation capacitance option version MAS6180B1.
Note 1
C
C_EXT
=C
0
MAS6180B5
VDD
Note 4
Optional
Control
for AGC on/hold
AON
Demodulator
&
Comparator
OUT
Receiver
Output
Note 5
RFIP
Ferrite
Antenna
VDD
QOP
QI
QOM
AGC Amplifier
RFIM
VDD
Power Supply/Biasing
VDD
VSS
PDN
AGC
C
AGC
10
µ
F
DEC
C
DEC
47 nF
VDD
VDD
1.4 V
GND
VDD
Note 3
Power Down /
Fast Startup
Control
Note 2
Figure 2.
Application circuit of external compensation capacitance option version MAS6180B5.
4 (14)
DA6180B.002
5 May, 2011
TYPICAL APPLICATION (Continued)
Note 1
Note 4
Optional
Control
for AGC on/hold
QI
QOM
AON
Demodulator
&
Comparator
OUT
Receiver
Output
MAS6180B5
VDD
Note 5
RFIP
Ferrite
Antenna
VDD
QOP
AGC Amplifier
RFIM
Antenna
Frequency
Selection
VDD
Power Supply/Biasing
VDD
VSS
PDN
AGC
C
AGC
10
µ
F
DEC
C
DEC
47 nF
1.4 V
GND
VDD
Note 3
Power Down /
Fast Startup
Control
VDD
VDD
Note 2
Figure 3.
Dual band application circuit of external compensation capacitance option version MAS6180B5. PMOS
switch transistor is used since RFIM input is biased close to VDD voltage.
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