ISO-9001 CERTIFIED BY DSCC
M.S.KENNEDY CORP.
FET INPUT DIFFERENTIAL
OPERATIONAL AMPLIFIER
801
(315) 701-6751
4707 Dey Road Liverpool, N.Y. 13088
FEATURES:
10 MHz full power bandwidth min.
650 Volts/µs slew rate min.
75 ns settling time to 0.1% max.
±100 mA output current min.
Replaces H0S-50
Fet Input
Available to DSCC SMD 5962-91574
MIL-PRF-38534 QUALIFIED
DESCRIPTION:
The MSK 801 is a high speed, FET input, differential amplifier that exhibits impressive DC characteristics. The FET input
of the MSK 801 produces extremely low input bias current, input offset voltage and input offset drift specifications. Wide
bandwidth, high input impedance, and high output current make it an ideal choice for many high speed/high frequency
applications. In addition, the MSK 801 offers the user external compensation, offset null and short circuit protection.
EQUIVALENT SCHEMATIC
EQUIVALENT SCHEMATIC
TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
D/A Converters
Buffer Amplifiers
High Speed Integrators
Sample and Hold Circuits
Video Drivers
1
2
3
4
5
6
1
PIN-OUT INFORMATION
+V
CC
Output Comp.
Comp./Bal.
Comp./Bal.
Inverting Input
Non-Inverting Input
12
11
10
9
8
7
+VC
Output
-V
C
-V
CC
Case
NC
Rev. B 6/04
ABSOLUTE MAXIMUM RATINGS
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See Curve
±200mA
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ELECTRICAL SPECIFICATIONS
±Vcc=±15V Unless Otherwise Specified
Group A
Parameter
Test Conditions
1
Quiescent Current
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
V
IN
=0V
2,3
V
IN
=0V
V
IN
=0V
1
2,3
1
2,3
Input Offset Current
Output Current
Output Voltage Swing
Full Power Bandwidth
Bandwidth (Small Signal)
Slew Rate Limit (Pulsed)
Large Signal Voltage Gain
Settling Time to 1%
Settling Time to 0.1%
1
1 2
2
MSK 801B/E
Typ.
±25
±27
±0.5
±10
±50
±0.2
10
0.1
Max.
±30
±32
±2
±25
±500
±10
500
5
-
-
-
-
-
-
55
75
-
-
-
-
-
-
-
75
Min.
-
-
-
-
-
-
-
-
MSK 801
Typ.
±25
-
±0.5
±10
±50
-
10
-
Max.
±35
-
±5
±50
±750
-
750
-
-
-
-
-
-
-
65
85
-
-
-
-
-
-
-
80
Units
mA
mA
mV
µV/°C
pA
nA
pA
nA
mA
V
MHz
MHz
V/µS
dB
nS
nS
nS
dB
dB
µVRMS
nV/√Hz
MHz
V/µS
°C/W
Subgroup Min.
-
-
-
-
-
-
-
-
1
2,3
R
L
=100Ω V
OUT
=±10V
R
L
=100Ω f
≤
10MHz
R
L
=100Ω V
O
=±10V
R
L
=510Ω
R
L
=100Ω V
O
=±10V
R
L
=1KΩ V
O
±10V
R
L
=100Ω V
IN
=10V
R
L
=100Ω V
IN
=10V
R
L
=100Ω V
IN
=10V
2
2
4
4
4
4
4
4
4
4
-
-
-
-
-
-
-
-
±100 ±120
±10
10
100
650
50
-
-
-
60
70
-
-
200
-
-
±11.5
12
125
750
70
40
60
200
70
80
1.5
40
250
700
65
±100 ±120
±10 ±11.5
8
90
550
50
-
-
-
55
65
-
-
200
-
-
12
125
750
70
40
60
200
70
80
1.5
40
250
700
65
Settling Time to 0.01%
1 2
Power Supply Rejection Ratio
Common Mode Rejection Ratio
Input Noise Voltage
2
∆V
CC
=±5V
∆V
IN
=±10V
f=10Hz to 1KHz
f=1KHz
Equivalent Input Noise
2
Gain Bandwidth Product
Slew Rate (Sine Wave)
Thermal Resistance
2
2
R
L
=510Ω AV=-20
R
L
=100Ω V
O
=±10V
Junction to Case @ 125°C
NOTES:
1
AV= -1, measured in false summing junction circuit.
2
Guaranteed by design but not tested. Typical parameters are representative of actual device performance
3
4
5
6
but are for reference only.
Industrial grade and "E" suffix devices shall be tested to subgroups 1 and 4 unless otherwise specified.
Military grade devices ("B" suffix) shall be 100% tested to subgroups 1,2,3 and 4.
Subgroups 5 and 6 testing available upon request.
Subgroup 1,4
T
A
=T
C
=+25°C
Subgroup 2
T
A
=T
C
=+125°C
Subgroup 3
T
A
=T
C
=-55°C
7
Consult DSCC SMD 5962-91574 for electrical specifications for devices purchased as such.
2
Rev. B 6/04
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±V
CC
Supply Voltage
+18V
Input Voltage
V
IN
±V
CC
Differential Input Voltage
±30V
Case Operating Temperature Range
T
C
(MSK 801)
-40°C to +125°C
(MSK801B/E)
-55°C to +125°C
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T
ST
Storage Temperature Range
T
LD
Lead Temperature Range
(10 Seconds Soldering)
P
D
Power Dissipation
I
OUT
Peak Output Current
-65°C to +150°C
300°C
APPLICATION NOTES
Heat Sinking
To determine if a heat sink is necessary for your applica-
tion and if so, what type, refer to the thermal model and
governing equation below.
Stability and Layout Considerations
As with all wideband devices, proper decoupling of the
power lines is extremely important. The power supplies
should be bypassed as near to pins 10 and 12 as possible
with a parallel grouping of a 0.01µf ceramic disc and a 4.7µf
tantalum capacitor. Wideband devices are also sensitive
to printed circuit board layout. Be sure to keep all runs as
short as possible, especially those associated with the sum-
ming junction, power lines and compensation pins.
Thermal Model:
Recommended External Component Selection
Guide Using External Rf
APPROXIMATE
DESIRED GAIN
1
RI(+)
500Ω
1KΩ
820Ω
0Ω
910Ω
0Ω
RI(-)
1KΩ
0Ω
1KΩ
910Ω
1KΩ
1KΩ
Rf
1KΩ
0Ω
4.99KΩ
3.6KΩ
10KΩ
9.1KΩ
R1
Cf
Governing Equation:
T
J=
P
D
x
(R
θJC
+
R
θCS
+
R
θJC
)
+
T
A
Where
T
J=
Junction Temperature
P
D=
Total Power Dissipation
R
θJC=
Junction to Case Thermal Resistance
R
θCS=
Case to Heat Sink Thermal Resistance
R
θSA=
Heat Sink to Ambient Thermal Resistance
T
C=
Case Temperature
T
A=
Ambient Temperature
T
S=
Sink Temperature
1
1
-1
+1
-5
+5
-10
+10
43Ω
0.01µf
43Ω 0.01µf
120Ω 0.01µf
120Ω 0.01µf
150Ω 0.01µf
150Ω 0.01µf
Example
:
This example demonstrates a worst case analysis for
the op-amp output stage. This occurs when the output volt-
age is 1/2 the power supply voltage. Under this condition,
maximum power transfer occurs and the output is under
maximum stress.
Conditions:
V
CC=
±16VDC
V
O=
±8Vp Sine Wave, Freq.=1KHz
R
L=
100Ω
For a worst case analysis we will treat the +8Vp sine
wave as an 8VDC output voltage.
1.) Find Driver Power Dissapation
P
D=
(VCC-VO) (VO/RL)
=
(16V-8V) (8V/100Ω)
=
0.64W
2.) For conservative design, set T
J=
+125°C
3.) For this example, worst case T
A=+
50°C
4.) R
θJC=
65°C/W from MSK 801 Data Sheet
5.) R
θCS=
0.15°C/W for most thermal greases
6.) Rearrange governing equation to solve for R
θSA
R
θSA=
((T
J-
T
A
)/P
D
)
-
(R
θJC
)
-
(R
θCS
)
=
((125°C
-
50°C)/0.64W)
-
65°C/W
-
0.15°C/W
=
117.2
-
65.15
=
52.0°C/W
1 The positive input resistor is selected to minimize offset
currents. The positve input can be grounded without a
resistor if desired.
2 This feedback capacitor will help compensate for stray
input capacitance. The value of this capacitor can be
dependent on individual applications. A 2 to 9 pf capacitor
is usually optimum for most applications.
Load Considerations
When determining the load an amplifier will see, the
capacative portion must be taken into consideration. For
an amplifier that slews at 1000V/µS, each pf will require 1
mA of output current. To minimize ringing with highly
capacitive loads, reduce the load time constant by adding
shunt resistance.
Case Connection
The MSK 801 has pin 8 internally connected to the
case. The case is not electrically connected to the internal
circuit. Pin 8 should be tied to a ground plane for shielding.
For special applications, consult factory.
3
Rev. B 6/04
APPLICATION NOTES CON'T
Slew Rate vs. Slew Rate Limit
SLEW RATE:
S=2πfVp; Slew rate is based upon the sinusoidal
linear response of the amplifier and is calculated from
the full power bandwidth frequency.
SLEW RATE LIMIT
dv/dt; The slew rate limit is based upon the amplifier's
response to a step input and is measured between 10%
and 90%. MSK measures Tr or Tf, whichever is greater
at ±10V
OUT
, R
L=
100Ω.
Offset Null
Typically the MSK 801 has an input offset voltage of
less than ±1 mV. If it is desirable to "null" the offset volt-
age, the circuit below is recommended.
R
P=
10KΩ
Definition of Settling Time
The time required for the output to come within a prede-
termined error band after application of a full scale step
input. This includes the time of delay, slew time and the
small signal settling of the amplifier.
Measuring Settling Time
The only accurate method of measuring settling time is by
the creation of a false summing junction and observing the
error band at that point.
The reasons for not using other methods are as follows:
Observation of settling at the actual summing junction adds
probe capacitance to the input and changes the entire re-
sponse of the system. (Probe capacitance almost doubles
the capacitance at the summing point.) Observing the out-
put is extremely difficult, as the 3% linearity of oscillo-
scopes, and reading inaccuracies, lead to a possible 5%
error. The false summing junction approach works well
bcause the amplifier is subtracting the output from the in-
put, and only 1/2 the actual error appears there.
Output Short Circuit Protection
The collectors of the output devices have been brought
out to pins 10 and 12 for short circuit protection, if desired.
A resistor can be inserted between +V
C
and +V
CC
pins,
and -V
C
and -V
CC
respectively. Resistor values can be se-
lected as follows:
R
SC
≅
(+)V
CC
= (-)V
CC
(+)I
SC
(-)I
SC
False Summing Junction Circuit
The addition of the these resistors reduces output volt-
age swing. Decoupling at ±V
C
can help to retain full swing
for transient pulses.
Problems: Because the amplifier is to be overdriven, 1/2
the input voltage can be expected to appear at the false
summing junction. Therefore, it is necessary to clamp that
point with diodes to limit the voltage excursion to avoid
overdriving the oscilloscope with the consequent recovery
time of the scope itself. The scope probe has capacitance
which significantly affects the settling time measurement.
Keep the associated resistors as low as possible to mini-
mize the RC time constants, and take into account the added
time created by the false summing junction. On the ranges
used for settling time measurement even the best real-time
scopes suffer from reduced bandwidth and relatively slow
settling; a sampling scope is convenient for these measure-
ments.
4
For normal operation and best overall response, short
+V
CC
and +V
C
and short -V
CC
and -V
C
together.
Rev. B 6/04
TYPICAL PERFORMANCE CURVES
5
Rev. B 6/04
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