A4952 and A4953
Full-Bridge DMOS PWM Motor Drivers
Features and Benefits
• Low R
DS(on)
outputs
• Overcurrent protection (OCP)
▫
Motor short protection
▫
Motor lead short to ground protection
▫
Motor lead short to battery protection
• Low Power Standby mode
• Adjustable PWM current limit
• Synchronous rectification
• Internal undervoltage lockout (UVLO)
• Crossover-current protection
• Fault output (A4952 only)
• Selectable retry (A4952 only)
Description
Designed for pulse width modulated (PWM) control of DC
motors, the A4952 and A4953 are capable of peak output
currents to ±2 A and operating voltages to 40 V.
Input terminals are provided for use in controlling the speed and
direction of a DC motor with externally applied PWM control
signals. Internal synchronous rectification control circuitry is
provided to lower power dissipation during PWM operation.
Internal circuit protection includes overcurrent protection,
motor lead short to ground or supply, thermal shutdown with
hysteresis, undervoltage monitoring of V
BB
, and crossover-
current protection.
The A4952 is provided in a low-profile 10-pin MSOP package
(suffix LY) and the A4953 is provided in a low-profile
8-pin SOICN package (suffix LJ). Both packages have an
exposed thermal pad, and are lead (Pb) free, with 100% matte tin
leadframe plating.
Packages:
10-pin MSOP
with exposed thermal pad
(LY package)
8-pin SOICN
with exposed thermal pad
(LJ package)
Not to scale
Functional Block Diagram
Load Supply
V
INT
A4952 only
RTRY
OSC
Charge
Pump
VBB
IN1
Control
Logic
Disable
TSD
UVLO
7V
OUT1
OUT2
IN2
GND
A4952 only
FLTn
VREF
LSS
÷
10
(Optional)
A4952-DS, Rev. 2
A4952 and
A4953
Selection Guide
Part Number
A4952ELYTR-T
A4953ELJTR-T
Full-Bridge DMOS PWM Motor Drivers
Packing
4000 pieces per 13-in. reel
3000 pieces per 13-in. reel
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Logic I/O Voltage Range
FLTn Sink Current
V
REF
Input Voltage Range
Sense Voltage (LSS pin)
Motor Outputs Voltage
Output Current
Transient Output Current
Operating Temperature Range
Maximum Junction Temperature
Storage Temperature Range
Symbol
V
BB
V
IN
I
FLTN
V
REF
V
S
V
OUT
I
OUT
i
OUT
T
A
T
J
(max)
T
stg
Duty cycle = 100%
T
W
< 500 ns
Temperature Range E
Notes
Rating
40
–0.3 to 6
10
–0.3 to 6
–0.5 to 0.5
–2 to 42
2
6
–40 to 85
150
–55 to 150
Unit
V
V
mA
V
V
V
A
A
°C
°C
°C
Thermal Characteristics
may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
LJ package, on 4-layer PCB based on JEDEC standard
Package Thermal Resistance
R
θJA
LJ package, on 2-layer PCB with 0.8 in
2
2-oz. copper each side
.
LY package, on 4-layer PCB based on JEDEC standard
LY package, (estimate) on 2-layer PCB with 1 in
2
2-oz. copper each side
.
*Additional thermal information available on the Allegro website.
Value
35
62
48
60
Unit
ºC/W
ºC/W
ºC/W
ºC/W
Terminal List Table
Pin-out Diagrams
GND
IN2
IN1
VREF
1
2
3
4
PAD
8 OUT2
7 LSS
6 OUT1
5 VBB
Name
FLTn
GND
IN1
IN2
LSS
OUT1
OUT2
PAD
RTRY
VBB
VREF
Number
A4952
1
10
4
3
8
7
9
–
2
6
5
A4953
–
1
3
2
7
6
8
–
–
5
4
Fault output, active low
Ground
Logic input 1
Logic input 2
Function
LJ Package (A4953)
FLTn 1
RTRY 2
IN2 3
IN1 4
VREF 5
PAD
10 GND
9 OUT2
8 LSS
7 OUT1
6 VBB
Power return – sense resistor connection
DMOS full bridge output 1
DMOS full bridge output 2
Exposed pad for enhanced thermal dissipation
Logic input
Load supply voltage
Analog input
LY Package (A4952)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
ELECTRICAL CHARACTERISTICS
Valid at T
J
= 25°C, unless otherwise specified
Characteristics
General
Load Supply Voltage Range
R
DS(on)
Sink + Source Total
Load Supply Current
Body Diode Forward Voltage
Logic I/O Inputs
V
IN(1)
Logic Input Voltage Range
Logic Input Pull-Down Resistance
Logic Input Current
Input Hysteresis
Logic I/O Inputs (A4952 only)
Retry Input Voltage
Retry Overcurrent Protection Pullup
Voltage
Retry Short Circuit Current
Fault Output Voltage
Fault Output Leakage Current
Timing
Crossover Delay
V
REF
Input Voltage Range
Current Gain
Blank Time
Constant Off-time
Standby Timer
Power-Up Delay
Protection Circuits
UVLO Enable Threshold
UVLO Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
V
BBUVLO
V
BBUVLOhys
T
JTSD
T
TSDhys
Temperature increasing
Recovery = T
JTSD
– T
TSDhys
V
BB
increasing
7
–
–
–
7.5
500
160
20
7.95
–
–
–
V
mV
°C
°C
t
COD
V
REF
V
REF
/ I
SS
, V
REF
= 5 V
A
V
t
BLANK
t
off
t
st
t
pu
IN1 = IN2 < V
IN(STANDBY)
V
REF
/ I
SS
, V
REF
= 2.5 V
V
REF
/ I
SS
, V
REF
= 1 V
50
0
9.5
9.0
8.0
2
16
–
–
400
–
–
–
–
3
25
1
–
500
5
10.5
10.0
10.0
4
34
1.5
30
ns
V
V/V
V/V
V/V
μs
μs
ms
μs
V
RTRY
V
RTRY(OC)
I
RTRY
V
RST
I
LK
RTRY pin = valid
RTRY pin = open
RTRY pin = GND
FLTn pin, I
OUT
= 1 mA
FLTn pin, no fault, pull-up to 5 V
–
–
–
–
–
–
3
10
–
–
200
–
–
0.5
1
mV
V
μA
V
μA
V
IN(0)
INx pins
INx pins
2.0
–
–
–
–
–
–
–
–
–
50
40
16
250
–
0.8
0.4
–
100
40
550
V
V
V
kΩ
μA
μA
mV
V
BB
R
DS(on)
I
BB
V
f
I
OUT
= |1.5 A|, T
J
= 25°C
I
OUT
= |1.5 A|, T
J
= 125°C
f
PWM
< 30 kHz
Low Power Standby mode
Source diode, I
f
= –1.5 A
Sink diode, I
f
= 1.5 A
8
–
–
–
–
–
–
–
0.8
1.3
10
–
–
–
40
1.0
1.6
–
10
1.5
1.5
V
Ω
Ω
mA
μA
V
V
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
V
IN(STANDBY)
INx pins, Low Power Standby mode
RR
R
LOGIC(PD)
V
IN
= 0 V = IN1 = IN2
I
IN(1)
I
IN(0
)
V
HYS
INx pins, V
IN
= 2.0 V
INx pins, V
IN
= 0.8 V
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Characteristic Performance
PWM Control Timing Diagram
V
IN(1)
IN1
GND
V
IN(1)
IN2
GND
+I
REG
I
OUT(x)
0A
-I
REG
Forward/
Fast Decay
Reverse/
Fast Decay
Forward/
Slow Decay
Reverse/
Slow Decay
PWM Control Truth Table
IN1
0
1
0
1
1
0
IN2
1
0
1
0
1
0
10×V
S
> V
REF
False
False
True
True
False
False
OUT1
L
H
H/L
L
L
Z
OUT2
H
L
L
H/L
L
Z
Reverse
Forward
Chop (mixed decay), reverse
Chop (mixed decay), forward
Brake (slow decay)
Coast, enters Low Power Standby mode after 1 ms
Function
Note: Z indicates high impedance.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A4952 and
A4953
Full-Bridge DMOS PWM Motor Drivers
Functional Description
Device Operation
The A4952 and A4953 are designed to operate DC motors. The
output drivers are all low-R
DS(on)
, N-channel DMOS drivers
that feature internal synchronous rectification to reduce power
dissipation. The current in the output full bridge is regulated with
fixed off-time pulse width modulated (PWM) control circuitry.
The IN1 and IN2 inputs allow two-wire control for the bridge.
Protection circuitry includes internal thermal shutdown, and pro-
tection against shorted loads, or against output shorts to ground
or supply. Undervoltage lockout prevents damage by keeping the
outputs off until the driver has enough voltage to operate nor-
mally.
Standby Mode
Low Power Standby mode is activated when both input (INx)
pins are low for longer than 1 ms. Low Power Standby mode
disables most of the internal circuitry, including the charge pump
and the regulator. When the A4952/A4953 is coming out of
standby mode, the charge pump should be allowed to reach its
regulated voltage (a maximum delay of 200
μs)
before any PWM
commands are issued to the device.
Internal PWM Current Control
Initially, a diagonal pair of source and sink FET outputs are
enabled and current flows through the motor winding and the
optional external current sense resistor, R
S
. When the voltage
across R
S
equals the comparator trip value, then the current sense
comparator resets the PWM latch. The latch then turns off the
sink and source FETs (Mixed Decay mode).
V
REF
The maximum value of current limiting is set by the selection of
R
Sx
and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
I
TripMAX
(A), which is set by:
I
TripMAX
=
V
REF
A
V
R
S
Overcurrent Protection
In the A4952, a current monitor will protect the IC from damage
due to output shorts. The internal Overcurrent Protection (OCP)
has the following features:
• Fault Output (FLTn pin). If a short is detected, the open drain
FLTn output signal goes low.
• Retry Input (RTRY pin). Sets the action taken by the IC to re-
spond to an OCP fault. If the RTRY pin is tied to GND, then the
outputs will be turned-on again after a 2-ms timeout, to check
if a fault condition remains. If the RTRY pin is left open, then
the fault will be latched, and the IC will disable the outputs. The
fault latch can only be cleared by coming out of Low Power
Standby mode or by cycling the power to VBB.
Note: The A4953 overcurrent protection behaves in the same
manner but the fault is latched and can only be reset by putting
the device into standby mode or by cycling the power to VBB.
During OCP events, Absolute Maximum Ratings may be
exceeded for a short period of time before the device latches.
Shutdown
If the die temperature increases to approximately 160°C, the full
bridge outputs will be disabled until the internal temperature falls
below a hysteresis, T
TSDhys
, of 20°C. Internal UVLO is present
on VBB to prevent the output drivers from turning-on below the
UVLO threshold.
Braking
The braking function is implemented by driving the device in
Slow Decay mode, which is done by applying a logic high to both
inputs, after a bridge-enable Chop command (see PWM Control
Truth Table). Because it is possible to drive current in both direc-
tions through the DMOS switches, this configuration effectively
shorts-out the motor-generated BEMF, as long as the Chop com-
mand is asserted. The maximum current can be approximated by
V
BEMF
/ R
L
. Care should be taken to ensure that the maximum
ratings of the device are not exceeded in worse case braking situ-
ations: high speed and high-inertia loads.
where V
REF
is the input voltage on the VREF pin (V) and R
S
is
the resistance of the sense resistor (Ω) on the LSS terminal.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
