A3988
Quad DMOS Full Bridge PWM Motor Driver
Features and Benefits
▪
▪
▪
▪
▪
▪
▪
▪
▪
▪
36 V output rating
4 full bridges
Dual stepper motor driver
High current outputs
3.3 and 5 V compatible logic supply
Synchronous rectification
Internal undervoltage lockout (UVLO)
Thermal shutdown circuitry
Crossover-current protection
Low profile QFN package
Description
The A3988 is a quad DMOS full-bridge driver capable of
driving up to two stepper motors or four DC motors. Each
full-bridge output is rated up to 1.2 A and 36 V. The A3988
includes fixed off-time pulse width modulation (PWM) current
regulators, along with 2- bit nonlinear DACs (digital-to-analog
converters) that allow stepper motors to be controlled in full,
half, and quarter steps, and DC motors in forward, reverse, and
coast modes. The PWM current regulator uses the Allegro
®
patented mixed decay mode for reduced audible motor noise,
increased step accuracy, and reduced power dissipation.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation.
Protection features include thermal shutdown with hysteresis,
undervoltage lockout (UVLO) and crossover current protection.
Special power up sequencing is not required.
Packages
Package EV, 36 pin QFN
0.90 mm nominal height
with exposed thermal pad
Approximate scale
The A3988 is supplied in two packages, EV and JP, with
exposed power tabs for enhanced thermal performance. The
EV is a 6 mm x 6 mm, 36 pin QFN package with a nominal
overall package height of 0.90 mm. The JP is a 7 mm × 7 mm
48 pin LQFP. Both packages are lead (Pb) free, with 100%
matte tin leadframe plating.
Package JP, 48 pin LQFP
with exposed thermal pad
0.1
μF
50 V
VCP
CP1
CP2
0.1
μF
50 V
VBB1
VBB2
100
μF
50 V
V
MOTOR
32 V
0.22
μF
50 V
PHASE1
I01
I11
PHASE2
Microprocessor
I02
I12
PHASE3
I03
I13
PHASE4
I04
I14
VREF1
V
REF
VREF2
VREF3
VREF4
VDD
V
DD
3.3 V
OUT1A
OUT1B
A3988
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
SENSE2
R
S2
SENSE1
R
S1
SENSE3
R
S3
SENSE4
R
S4
Bipolar Stepper Motors
Figure 1. Typical application circuit
A3988DS, Rev. 9
A3988
Selection Guide
Part Number
A3988SEV-T
A3988SEVTR-T
A3988SJPTR-T
Quad DMOS Full Bridge PWM Motor Driver
Package
36 pin QFN with exposed thermal pad
36 pin QFN with exposed thermal pad
48 pin LQFP with exposed thermal pad
61 pieces per tube
1500 pieces per reel
1500 pieces per reel
Packing
Absolute Maximum Ratings
Characteristic
Load Supply Voltage
Logic Supply Voltage
Output Current
Symbol
V
BB
Pulsed t
w
< 1
μs
V
DD
I
OUT
May be limited by duty cycle, ambient temperature, and heat sinking. Under
any set of conditions, do not exceed the specified current rating or a Junction
Temperature of 150°C.
Pulsed t
w
< 1
μs
Logic Input Voltage Range
SENSEx Pin Voltage
VREFx Pin Voltage
Operating Temperature Range
Junction Temperature
Storage Temperature Range
V
IN
V
SENSEx
Pulsed t
w
< 1
μs
V
REFx
T
A
T
J
(max)
T
stg
Range S
Notes
Rating
-0.5 to 36
38
–0.4 to 7
1.2
Units
V
V
V
A
2.8
–0.3 to 7
0.5
2.5
2.5
–20 to 85
150
–40 to 125
A
V
V
V
V
ºC
ºC
ºC
Thermal Characteristics (may require derating at maximum conditions)
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions
EV package, 4 layer PCB based on JEDEC standard
JP package, 4 layer PCB based on JEDEC standard
Min. Units
27
23
ºC/W
ºC/W
Power Dissipation versus Ambient Temperature
5500
5000
4500
4000
JP Package
4-layer PCB
(R
JA
= 23 ºC/W)
Power Dissipation, P
D
(mW)
3500
3000
2500
2000
1500
1000
500
0
25
50
75
100
125
Temperature (°C)
150
175
EV Package
4-layer PCB
(R
JA
= 27 ºC/W)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Block Diagram
0.1
μF
50 V
0.1
μF
50 V
100
μF
50 V
0.22
μF
50 V
To
V
BB2
VBB1
VCP
CP1
CP2
VDD
DMOS
FULL-BRIDGE 1
V
CP
VBB1
OSC
CHARGE PUMP
OUT1A
PHASE1
I01
I11
PHASE2
I02
I12
GATE
DRIVE
VBB1
DMOS
FULL-BRIDGE 2
Control Logic
Bridges 1 and 2
OUT1B
SENSE1
Sense1
VREF1
3
-
+
PWM Latch
BLANKING
OUT2A
VREF2
3
Sense2
+
PWM Latch
BLANKING
OUT2B
-
PHASE3
I03
I13
PHASE4
I04
I14
GATE
DRIVE
Sense3
VBB2
PWM Latch
BLANKING
SENSE3
Control Logic
Bridges 3 and 4
V
CP
Sense2
SENSE2
VBB2
DMOS
FULL-BRIDGE 3
OUT3A
OUT3B
+
VREF3
3
-
Sense3
DMOS
FULL-BRIDGE 4
VREF4
3
Sense4
OUT4A
OUT4B
GND
GND
+
PWM Latch
BLANKING
Sense4
SENSE4
-
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A3988
Quad DMOS Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS
1
, valid at T
A
= 25°C, V
BB
= 36 V, unless otherwise noted
Characteristics
Load Supply Voltage Range
Logic Supply Voltage Range
VDD Supply Current
Output On Resistance
V
f
, Outputs
Output Leakage
VBB Supply Current
Control Logic
Logic Input Voltage
Logic Input Current
Input Hysteresis
V
IN(1)
V
IN(0)
I
IN
V
hys
PWM change to source on
Propagation Delay Times
t
pd
PWM change to source off
PWM change to sink on
PWM change to sink off
Crossover Delay
Blank Time
VREFx Pin Input Voltage Range
VREFx Pin Reference Input Current
Current Trip-Level Error
3
Protection Circuits
VBB UVLO Threshold
VBB Hysteresis
VDD UVLO Threshold
VDD Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
1
For
2
Typical
Symbol
V
BB
V
DD
I
DD
R
DS(on)
Operating
Operating
Test Conditions
Min.
8.0
3.0
–
–
–
–
–20
–
Typ.
2
–
–
7
700
700
–
–
–
Max.
36
5.5
10
800
800
1.3
20
8
Units
V
V
mA
mΩ
mΩ
V
μA
mA
Source driver, I
OUT
= –1.2 A, TJ = 25°C
Sink driver, I
OUT
= 1.2 A, TJ = 25°C
I
OUT
= 1.2 A
Outputs, V
OUT
= 0 to V
BB
I
OUT
= 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
I
DSS
I
BB
0.7×V
DD
–
V
IN
= 0 to 5 V
–20
150
350
35
350
35
300
0.7
Operating
V
REF
= 1.5
V
REF
= 1.5, phase current = 100%
V
REF
= 1.5, phase current = 67%
V
REF
= 1.5, phase current = 33%
0.0
–
–5
–5
–15
7.3
400
V
DD
rising
2.65
75
155
–
–
–
<1.0
300
550
–
550
–
425
1
–
–
–
–
–
7.6
500
2.8
105
165
15
–
0.3×V
DD
20
500
1000
300
1000
250
1000
1.3
1.5
±1
5
5
15
7.9
600
2.95
125
175
–
V
V
μA
mV
ns
ns
ns
ns
ns
μs
V
μA
%
%
%
V
mV
V
mV
°C
°C
t
COD
t
BLANK
V
REFx
I
REF
V
ERR
V
UV(VBB)
V
UV(VBB)hys
V
UV(VDD)
V
UV(VDD)hys
T
JTSD
T
JTSDhys
V
BB
rising
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3
V
ERR
= [(V
REF
/3) – V
SENSE
] / (V
REF
/3).
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A3988
Quad DMOS Full Bridge PWM Motor Driver
Functional Description
Device Operation
The A3988 is designed to operate two
stepper motors, four DC motors, or one stepper and two DC
motors. The currents in each of the output full-bridges, all
N-channel DMOS, are regulated with fixed off-time pulse width
modulated (PWM) control circuitry. Each full-bridge peak current
is set by the value of an external current sense resistor, R
Sx
, and a
reference voltage, V
REFx
.
If the logic inputs are pulled up to V
DD
, it is good practice to use
a high value pull-up resistor in order to limit current to the logic
inputs, should an overvoltage event occur. Logic inputs include:
PHASEx, I0x, and I1x.
Note: It is critical to ensure that the maximum rating of
500
mV
on each SENSEx pin is not exceeded.
Fixed Off-Time
The internal PWM current control circuitry
uses a one shot circuit to control the time the drivers remain off.
The one shot off-time, t
off
, is internally set to 30
μs.
Blanking
This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions, due to reverse recovery
currents of the clamp diodes, or to switching transients related to
the capacitance of the load. The stepper blank time, t
BLANK
, is
approximately 1
s.
Internal PWM Current Control
Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, I
TRIP
. Initially, a diagonal pair
of source and sink DMOS outputs are enabled and current flows
through the motor winding and R
Sx
. When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
The maximum value of current limiting is set by the selection of
R
S
and the voltage at the VREF input with a transconductance
function approximated by:
I
TripMax
= V
REF
/ (3×R
S
)
Each current step is a percentage of the maximum current,
I
TripMax
. The actual current at each step I
Trip
is approximated by:
I
Trip
= (% I
TripMax
/ 100) I
TripMax
where % I
TripMax
is given in the Step Sequencing table.
Control Logic
Communication is implemented via the indus-
try standard I1, I0, and PHASE interface. This communication
logic allows for full, half, and quarter step modes. Each bridge
also has an independent V
REF
input so higher resolution step
modes can be programmed by dynamically changing the voltage
on the VREFx pins.
Charge Pump (CP1 and CP2)
The charge pump is used to
generate a gate supply greater than the V
BB
in order to drive the
source-side DMOS gates. A 0.1
F
ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes. A 0.1
F
ceramic capacitor is required between VCP and VBBx to act as a
reservoir to operate the high-side DMOS devices.
Shutdown
In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
