1GB, 2GB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
REGISTERED QUAD-RANK
DDR SDRAM DIMM
Features
• 184-pin, dual in-line memory modules (DIMM),
organized as four module ranks
• Fast data transfer rates: PC1600 and PC2100
• Utilizes 200 MT/s and 266 MT/s TwinDie
Ô
DDR or
Stacked TSOP DDR SDRAM components
• ECC, 1-bit error detection and correction
• Low-Profile PCB design
• Registered inputs with one-clock delay
• Phase-lock loop (PLL) clock driver to minimize
loading
• 1GB (128 Meg x 72) and 2GB (256 Meg x 72)
• 2.5V I/O (SSTL_2 compatible)
• V
DD
= V
DD
Q= +2.5V
• V
DDSPD
= +2.3V to +3.6V
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Selectable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 7.8125µs maximum average periodic refresh
interval
• Serial Presence Detect (SPD) with EEPROM
• Selectable READ CAS latency
• Gold edge connectors
For the latest data sheet, please refer to the Micron
â
Web
site:
www.micron.com/moduleds
MT36VDDS12872D – 1GB (ADVANCE
‡
),
MT36VDDT12872D – 1GB, MT36VDDS25672D – 2GB
(ADVANCE
‡
), MT36VDDT25672D – 2GB
Figure 1: 184-Pin Low Profile DIMM
(MO-206)
OPTIONS
MARKING
• Package
184-Pin DIMM (Standard)
G
184-Pin DIMM (Lead-free)
Y
• Memory Clock/Data Frequency, CAS Latency
1
7.5ns (133 MHz)/266 MT/s, CL = 2
-262
2
7.5ns (133 MHz)/266 MT/s, CL = 2
-26A
2
7.5ns (133 MHz)/266 MT/s, CL = 2.5
-265
2
8ns (100 MHz)/200 MT/s, CL = 2
-202
2
NOTE:
1. CL = Device CAS (READ) Latency; registered
mode adds one clock cycle to CL due to the input
register.
2. Contact factory for availability.
Table 1:
Address Table
MT36VDDS12872D
MT36VDDT12872D
8K
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 8
1K (A0–A9)
4 (S0#-S3#)
MT36VDDS25672D
8K
8K (A0–A12)
4 (BA0, BA1)
64 Meg x 8
2K (A0–A9, A11)
4 (S0#-S3#)
MT36VDDT25672D
8K
8K (A0–A12)
4 (BA0, BA1)
64 Meg x 8
2K (A0–A9, A11)
4 (S0#-S3#)
8K
8K (A0–A12)
4 (BA0, BA1)
32 Meg x 8
1K (A0–A9)
4 (S0#-S3#)
Refresh Count
Row Addressing
Device Bank Addressing
Base Device Configuration
Column Addressing
Module Rank Addressing
128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM
DD36C128_256x72DG_C.fm - Rev. C 7/03 EN
1
©2003 Micron Technology, Inc. All rights reserved.
‡
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
1GB, 2GB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
1GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
2GB
CONFIGURATION
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
128 Meg x 72
128 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
256 Meg x 72
128 Meg x 72
128 Meg x 72
MODULE
BANDWIDTH
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
1.6 GB/s
1.6 GB/s
MEMORYCLOCK/
DATA RATE
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
10ns/200 MT/s
10ns/200 MT/s
LATENCY
(CL -
t
RCD -
t
RP)
2-3-3
2-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2.5-3-3
2-2-2
2-2-2
2.5-3-3
2-2-2
2-2-2
2-3-3
2-3-3
2-2-2
2-2-2
2.5-3-3
2.5-3-3
2-2-2
2-2-2
PART NUMBER
MT36VDDS12872DG-26A__
MT36VDDS12872DY-26A__
MT36VDDS12872DG-262__
MT36VDDS12872DY-262__
MT36VDDS12872DG-265__
MT36VDDS12872DY-265__
MT36VDDS12872DG-202__
MT36VDDS12872DY-202__
MT36VDDT12872DG-26A__
MT36VDDT12872DY-26A__
MT36VDDT12872DG-262__
MT36VDDT12872DY-262__
MT36VDDT12872DG-265__
MT36VDDT12872DY-265__
MT36VDDT12872DG-202__
MT36VDDT12872DY-202__
MT36VDDS25672DG-26A__
MT36VDDS25672DY-26A__
MT36VDDS25672DG-262__
MT36VDDS25672DY-262__
MT36VDDS25672DG-265__
MT36VDDS25672DY-265__
MT36VDDS25672DG-202__
MT36VDDS25672DY-202__
MT36VDDT25672DG-26A__
MT36VDDT25672DY-26A__
MT36VDDT25672DG-262__
MT36VDDT25672DY-262__
MT36VDDT25672DG-265__
MT36VDDT25672DG-265__
MT36VDDT25672DG-202__
MT36VDDT25672DY-202__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT36VDDT12872DY-265A1.
128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM
DD36C128_256x72DG_C.fm - Rev. C 7/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
Table 3:
Pin Assignment
(184-Pin DIMM Front)
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
DQ19
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
CB0
CB1
V
DD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
V
SS
CB3
BA1
DQ32
V
DD
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
V
DD
WE#
DQ41
CAS#
V
SS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
V
DD
S2#
DQ48
DQ49
V
SS
DNU
DNU
V
DD
DQS6
DQ50
DQ51
V
SS
NC
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
NC
SDA
SCL
Table 4:
Pin Assignment
(184-Pin DIMM Back)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
RESET#
V
SS
DQ8
DQ9
DQS1
V
DD
DNU
DNU
V
SS
DQ10
DQ11
CKE0
V
DD
DQ16
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
93
V
SS
116
V
SS
139
V
SS
162 DQ47
94
DQ4
117 DQ21
140
DQS17/DM8
163
S3#
95
DQ5
118
A11
141
A10
164
V
DD
96
V
DD
119
DQS11/DM2
142
CB6
165 DQ52
97
DQS9/DM0
120
V
DD
143
V
DD
166 DQ53
98
DQ6
121 DQ22
144
CB7
167
DNU
99
DQ7
122
A8
145
V
SS
168
V
DD
100
V
SS
123 DQ23 146 DQ36
169
DQS15/DM6
101
NC
124
V
SS
147 DQ37 170 DQ54
171 DQ55
102
NC
125
A6
148
V
DD
103
NC
126 DQ28
149
DQS13/DM4
172
V
DD
104
V
DD
127 DQ29 150 DQ38
173
NC
105 DQ12
128
V
DD
151 DQ39 174 DQ60
106 DQ13
129
DQS12/DM3
152
V
SS
175 DQ61
107
DQS10/DM1
130
A3
153 DQ44
176
V
SS
108
V
SS
131 DQ30 154 RAS# 177
DQS16/DM7
109 DQ14
132
V
SS
155 DQ45 178 DQ62
110 DQ15 133 DQ31
156
V
DD
179 DQ63
111 CKE1 134
CB4
157
S0#
180
V
DD
112
V
DD
135
CB5
158
S1#
181
SA0
113
NC
136
V
DD
159
DQS14/DM5
182
SA1
114 DQ20
137
CK0
160
V
SS
183
SA2
115
A12
138 CK0#
161 DQ46
184 V
DDSPD
Figure 2: 184-Pin DIMM Pin Locations
Low Profile Quad-Rank
FRONT VIEW
U19
U1
U2
U3
U4
U5
U6
U7
U8
U9
U20
PIN 1
PIN 52
PIN 53
PIN 92
BACK VIEW
U21
U10
U11
U12
U13
U14
U15
U16
U17
U18
U22
PIN 184
PIN 145
PIN 144
PIN 93
Indicates a V
DD
or V
DD
Q pin
Indicates a V
SS
pin
128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM
DD36C128_256x72DG_C.fm - Rev. C 7/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
Table 5:
Pin Descriptions
SYMBOL
V
REF
WE#, CAS#, RAS#
CS0–CS4
CK0, CK0#
TYPE
Input
Input
Input
Input
DESCRIPTION
SSTL_2 reference voltage.
Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.
Chip Select.
Clock: CK and CK# are differential clock inputs. All address
and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V
DD
is applied.
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which register
(mode register or extended mode register) is loaded during
the LOAD MODE REGISTER command.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Asynchronously forces all register outputs LOW when RESET#
is LOW. This signal can be used during power-up to ensure
CKE is LOW and SDRAM DQs are High-Z.
Data I/Os: Check bits. ECC 1-bit error detection and correction.
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
1
63, 65, 154
71, 157, 158, 163
137, 138
21, 111
CKE0 - CKE1
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48,
115, 118, 122, 125, 130,
141
A0-A12
Input
91
SDA
Input/Output
92
181, 182, 183
10
SCL
SA0-SA2
RESET#
Input
Input
Input
44, 45, 49, 51, 134, 135,
142, 144
CB0-CB7
Input/Output
128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM
DD36C128_256x72DG_C.fm - Rev. C 7/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
1GB, 2GB (x72, ECC)
184-PIN REGISTERED DDR SDRAM DIMM
Table 5:
Pin Descriptions
SYMBOL
DQS0-DQS17
TYPE
Input/Output
DESCRIPTION
Data Strobe: DQS0-DQS8, Output with READ data, input with
WRITE data. DQS is edge-aligned with READ data, centered in
WRITE data. Used to capture data. Data Mask: DQS9-DQS17
function as DM0-DM8 to mask WRITE data when when HIGH.
Data I/Os: Data bus.
Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
5, 14, 25, 36, 47, 56, 67,
78, 86, 97, 107, 119,
129, 140, 149, 159,
169, 177
2, 4, 6, 8, 12, 13, 19, 20,
23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,
105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
7, 15, 22, 30, 38, 46, 54,
62, 70, 77, 85, 96,104,
108, 112, 120, 128, 136,
143, 148, 156, 164, 168,
172, 180
3, 11, 18, 26, 34, 42, 50,
58, 66, 74, 81, 89, 93,
100, 116, 124, 132, 139,
145, 152, 160, 176
184
9, 82, 90, 101, 102, 103,
113, 173
16, 17, 75, 76, 167
DQ0-DQ63
Input/
Output
V
DD
Supply
Power Supply: +2.5V ±0.2V.
V
SS
Supply
Ground.
V
DDSPD
NC
DNU
Supply
—
—
Serial EEPROM positive power supply: +2.3V to +3.6V.
No Connect: These pins should be left unconnected.
Do Not Use: These pins are not connected on this module but
are assigned pins on other modules in this product family.
128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM
DD36C128_256x72DG_C.fm - Rev. C 7/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
