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5962F9679901V9A

产品描述74 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14, DIE-14
产品类别逻辑    逻辑   
文件大小212KB,共25页
制造商Renesas(瑞萨电子)
官网地址https://www.renesas.com/
下载文档 详细参数 选型对比 全文预览

5962F9679901V9A概述

74 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14, DIE-14

5962F9679901V9A规格参数

参数名称属性值
是否Rohs认证不符合
厂商名称Renesas(瑞萨电子)
零件包装代码DIE
包装说明DIE, DIE OR CHIP
针数14
Reach Compliance Codecompliant
系列74
JESD-30 代码S-XUUC-N14
JESD-609代码e0
负载电容(CL)50 pF
逻辑集成电路类型D FLIP-FLOP
最大I(ol)0.00005 A
位数1
功能数量2
端子数量14
最高工作温度125 °C
最低工作温度-55 °C
输出极性COMPLEMENTARY
封装主体材料UNSPECIFIED
封装代码DIE
封装等效代码DIE OR CHIP
封装形状SQUARE
封装形式UNCASED CHIP
峰值回流温度(摄氏度)NOT SPECIFIED
电源5 V
Prop。Delay @ Nom-Sup20 ns
传播延迟(tpd)20 ns
认证状态Not Qualified
筛选级别MIL-PRF-38535 Class V
最大供电电压 (Vsup)5.5 V
最小供电电压 (Vsup)4.5 V
标称供电电压 (Vsup)5 V
表面贴装YES
技术CMOS
温度等级MILITARY
端子形式NO LEAD
端子位置UPPER
处于峰值回流温度下的最长时间NOT SPECIFIED
总剂量300k Rad(Si) V
触发器类型POSITIVE EDGE
最小 fmax79 MHz

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REVISIONS
LTR
A
B
C
DESCRIPTION
Changes in accordance with NOR 5962-R338-97.
Changes in accordance with NOR 5962-R049-99.
Update boilerplate to MIL-PRF-38535 and updated appendix A. Editorial
changes throughout. - tmh
DATE (YR-MO-DA)
97-09-30
99-04-05
00-07-17
APPROVED
Monica L. Poelking
Monica L. Poelking
Monica L. Poelking
REV
SHEET
REV
SHEET
REV STATUS
OF SHEETS
PMIC N/A
C
15
C
16
C
17
C
18
REV
SHEET
PREPARED BY
Thanh V. Nguyen
C
19
C
20
C
21
C
1
C
22
C
2
C
23
C
3
C
24
C
4
C
5
C
6
C
7
C
8
C
9
C
10
C
11
C
12
C
13
C
14
STANDARD
MICROCIRCUIT
DRAWING
THIS DRAWING IS AVAILABLE
FOR USE BY ALL
DEPARTMENTS
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
CHECKED BY
Thanh V. Nguyen
APPROVED BY
Monica L. Poelking
DRAWING APPROVAL DATE
96-03-25
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43216
MICROCIRCUIT, DIGITAL, RADIATION
HARDENED ADVANCED CMOS, DUAL D FLIP-
FLOP WITH SET AND RESET, MONOLITHIC
SILICON
SIZE
A
SHEET
CAGE CODE
AMSC N/A
REVISION LEVEL
C
67268
1 OF
24
5962-96799
DSCC FORM 2233
APR 97
DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.
5962-E367-00

5962F9679901V9A相似产品对比

5962F9679901V9A 5962F9679902VCX 5962F9679902VXX 5962F9679901VXX 5962F9679902VCC 5962F9679902V9A 5962F9679902VXC 5962F9679901VCX
描述 74 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14, DIE-14 AC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14, CERAMIC, DIP-14 AC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC, DFP-14 74 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14 74 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14 74 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC14, DIE-14 74 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14 74 SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP14
零件包装代码 DIE DIP DFP DFP DIP DIE DFP DIP
包装说明 DIE, DIE OR CHIP DIP, DFP, DFP, DIP, DIP14,.3 DIE, DFP, FL14,.3 DIP,
针数 14 14 14 14 14 14 14 14
Reach Compliance Code compliant unknown unknown compliant not_compliant unknown not_compliant compliant
系列 74 AC AC 74 AC 74 AC 74
JESD-30 代码 S-XUUC-N14 R-CDIP-T14 R-CDFP-F14 R-CDFP-F14 R-CDIP-T14 S-XUUC-N14 R-CDFP-F14 R-CDIP-T14
逻辑集成电路类型 D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
位数 1 1 1 1 1 1 1 1
功能数量 2 2 2 2 2 2 2 2
端子数量 14 14 14 14 14 14 14 14
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
输出极性 COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
封装主体材料 UNSPECIFIED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED UNSPECIFIED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装代码 DIE DIP DFP DFP DIP DIE DFP DIP
封装形状 SQUARE RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR SQUARE RECTANGULAR RECTANGULAR
封装形式 UNCASED CHIP IN-LINE FLATPACK FLATPACK IN-LINE UNCASED CHIP FLATPACK IN-LINE
传播延迟(tpd) 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns 20 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
筛选级别 MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V MIL-PRF-38535 Class V
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 YES NO YES YES NO YES YES NO
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
端子形式 NO LEAD THROUGH-HOLE FLAT FLAT THROUGH-HOLE NO LEAD FLAT THROUGH-HOLE
端子位置 UPPER DUAL DUAL DUAL DUAL UPPER DUAL DUAL
总剂量 300k Rad(Si) V 300k Rad(Si) V 300k Rad(Si) V 300k Rad(Si) V 300k Rad(Si) V 300k Rad(Si) V 300k Rad(Si) V 300k Rad(Si) V
触发器类型 POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
最小 fmax 79 MHz 79 MHz 79 MHz 79 MHz 79 MHz 79 MHz 79 MHz 79 MHz
JESD-609代码 e0 e4 e4 - e0 e0 e0 -
端子面层 - GOLD GOLD - Tin/Lead (Sn/Pb) TIN LEAD Tin/Lead (Sn/Pb) -
Base Number Matches - 1 1 1 1 1 1 1

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