IDT74FCTL2828T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT BUFFERS
EXTENDED COMMERCIAL TEMPERATURE RANGE
HIGH-SPEED CMOS
BUS INTERFACE
10-BIT BUFFER
FEATURES:
−
−
−
−
−
−
−
−
−
−
−
Pin and function compatible to the Quality QS74FCT Family
Extended commercial range of –40°C to +85°C
CMOS power levels: <7.5mW static
Available in PDIP, SOIC, and QSOP packages
Undershoot clamp diodes on all inputs
True TTL input and output compatibility
Ground bounce controlled outputs
Reduced output swing of 0 to 3.5V
Built-in 25Ω series resistor outputs reduce reflection and other
system noise
A and B speed grades with 5ns t
PD
for B
I
OL
= 12mA
IDT74FCTL2828T
DESCRIPTION:
The IDT74FCTL2828T is a 10-bit buffer with 3-state outputs, ideal for
driving high capacitance loads such as memory and address buses. The
2828 device is a 25Ω resistor output version, useful for driving transmission
lines and reducing system noise. The 2828 series parts can replace the
828 series to reduce noise in an existing design. All inputs have clamp
diodes for undershoot noise suppression. All outputs have ground bounce
suppression. Outputs will not load an active bus when Vcc is removed from
the device.
FUNCTIONAL BLOCK DIAGRAM
Di
OE1
OE2
25
Ω
Yi
EXTENDED COMMERCIAL TEMPERATURE RANGE
1
c
1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-5259/-
IDT74FCTL2828T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT BUFFER
EXTENDED COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
1
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
P24-1
SO24-2
SO24-8
ABSOLUTE MAXIMUM RATINGS
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
OE
2
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
(1)
Unit
V
°C
mA
mA
mA
FCTL
Max.
– 0.5 to +7
– 65 to +150
120
– 20
– 50
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
FCTL
NOTE:
1. This parameter is measured at characterization but not tested.
PDIP/ SOIC/ QSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
Dx
Yx
OEx
I/O
I
O
I
Description
Data Inputs
Data Outputs
Output Enables
FUNCTION TABLE
(1)
Inputs
OE1
L
L
H
—
OE2
L
L
—
H
Dx
L
H
—
—
Outputs
Yx
H
L
Hi-Z
Hi-Z
Function
Enabled
Enabled
High-Impedance
High-Impedance
NOTE:
1. H = HIGH
L = LOW
Z = High-Impedance
2
IDT74FCTL2828T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT BUFFERS
EXTENDED COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
∆V
T
I
IH
I
IL
I
OZ
I
OR
V
IC
V
OH
V
OL
R
OUT
Parameter
Input HIGH Level
Input LOW Level
Input Hysteresis
Input HIGH Current
Input LOW Current
Off-State Output Current (Hi-Z)
Current Drive
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage - 25Ω
Output Resistance - 25Ω
V
CC
= Max.
V
CC
= Max., V
OUT
= 2.0V
(2, 3)
V
CC
= Min., I
IN
= –18mA, T
A
= 25
°
C
(3)
V
CC
= Min.
V
CC
= Min.
V
CC
= Min.
I
OH
= -15mA
I
OL
= 12mA
I
OL
= 12mA
0
≤
V
IN
≤
Vcc
—
50
—
2.4
—
20
—
—
–0.7
—
—
28
±5
—
–1.2
—
0.5
40
µA
mA
V
V
V
Ω
Test Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
TLH
- V
THL
for all inputs
V
CC
= Max.
0
≤
V
IN
< Vcc
Min.
2
—
—
—
Typ.
(1)
—
—
0.2
—
Max.
—
0.8
—
±5
Unit
V
V
V
µA
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
3. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Extended Commercial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
I
CC
Parameter
Quiescent Power Supply Current
Test Conditions
(1)
V
CC
= Max.
freq = 0
0V
≤
V
IN
≤
0.2V or
Vcc-0.2V
≤
V
IN
≤
Vcc
V
CC
= Max.
V
IN
= 3.4V
(2)
freq = 0
V
CC
= Max.
Outputs Open and Enabled
One Bit Toggling
50% Duty Cycle
Other inputs at GND or Vcc
(3,4)
Min.
—
Max.
1.5
Unit
mA
∆I
CC
Supply Current per Input TTL Inputs HIGH
—
2
mA
I
CCD
Supply Current per Input per MHz
—
0.25
mA/MHz
FCTL
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (V
IN
= 3.4V).
3. For flip-flops, Q
CCD
is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of
device power consumption only and does not include power to drive load capacitance or tester capacitance.
4. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
3
IDT74FCTL2828T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT BUFFER
EXTENDED COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
74FCTL2828AT
Symbol
t
PHL
t
PLH
t
PHL
t
PLH
t
PZH
t
PZL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
PHZ
t
PLZ
Parameter
(2)
Propagation Delay
Dx to Yx
Propagation Delay
Dx to Yx
(2,3)
Output Enable Time
OEx
to Yx
Output Enable Time
OEx
to Yx
(2,3)
Output Disable Time
OEx
to Yx
(2,4)
Output Disable Time
OEx
to Yx
(2)
Min.
—
—
—
—
—
—
Max.
7.5
17
12
23
9
10
74FCTL2828BT
Min.
—
—
—
—
—
—
Max.
5
—
8
—
6
7
Unit
ns
ns
ns
ns
ns
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. This parameter is guaranteed by design but not tested.
3. C
LOAD
= 300pF
4. C
LOAD
= 5pF
4
IDT74FCTL2828T
HIGH-SPEED CMOS BUS INTERFACE 10-BIT BUFFERS
EXTENDED COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
V
IN
Pulse
Generator
D.U.T.
50pF
R
T
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Open
FCTL
7.0V
Switch
Closed
V
OUT
500
Ω
C
L
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
O ctal lin k
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
SU
TIM ING
INPUT
ASYNCHRONOUS C ONTROL
PRES ET
CLEAR
ETC.
SYNCHRO NOUS CONTRO L
PRES ET
CLEAR
CLOCK ENABLE
ETC.
t
REM
t
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
O ctal lin k
PULSE WIDTH
LO W -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
O ctal lin k
1.5V
1.5V
t
SU
t
H
PROPAGATION DELAY
SAM E PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE P HASE
INPUT TRANSITION
t
PH L
t
PH L
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
O ctal lin k
ENABLE AND DISABLE TIMES
ENAB LE
DISA BLE
3V
CO NTROL
INPUT
t
PZL
OUTPUT
NO RM A LLY
LO W
SW ITCH
CLOSE D
t
PZH
OUTPUT
NO RM A LLY
HIGH
SW ITCH
OPEN
3.5V
1.5V
0.3V
t
PHZ
0.3V
1.5V
0V
0V
O ctal lin k
1.5V
t
PLZ
0V
3.5V
V
OL
V
OH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
5
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