Features
•
Core
– ARM926EJ-S™ ARM
®
Thumb
®
Processor running up to 400 MHz @ 1.0V +/- 10%
– 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit
Memories
– One 128-Kbyte internal ROM embedding secure bootstrap routine
– One 32-Kbyte internal SRAM, single-cycle access at system speed
–
32-bit
External Bus Interface supporting 8-bank DDR2/LPDDR, SDR/LPSDR, Static
Memories
– MLC/SLC NAND Controller, with up to 24-bit Programmable Multi-bit Error
Correcting Code (PMECC)
– System running up to 133 MHz
– Power-on Reset, Reset Controller, Shut Down Controller, Periodic Interval Timer,
Watchdog Timer and Real Time Clock
– Boot Mode Select Option, Remap Command
– Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators
– Selectable 32768 Hz Low-power Oscillator, 16 MHz Oscillator,
one PLL for the
system and one PLL
optimized for USB
– Six
32-bit-layer
AHB Bus Matrix
– Dual Peripheral Bridge with dedicated programmable clock
– One dual port 8-channel DMA Controller
– Advanced Interrupt Controller and Debug Unit
– Two Programmable External Clock Signals
Low Power Mode
– Shut Down Controller with four 32-bit battery backup registers
– Clock Generator and Power Management Controller
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
Peripherals
– LCD Controller
– USB Device Full Speed with dedicated On-Chip Transceiver
– USB Host Full Speed with dedicated On-Chip Transceiver
– One High speed SD card and SDIO Host Controller
– Two Master/Slave Serial Peripheral Interfaces
– Two Three-channel 32-bit Timer/Counters
– One Synchronous Serial Controller
– One Four-channel 16-bit PWM Controller
– Two Two-wire Interfaces
– Four USARTs plus two UARTs
– One 12-channel 10-bit Analog-to-Digital Converter with up to 5-wire resistive
Touch screen support
– Write Protected Registers
Cryptography
– TRNG True Random Number Generator compliant with NIST Special Publication
800-22
– AES 256-, 192-, 128-bit Key Algorithm compliant with FIPS Publication 197
– SHA (SHA1 and SHA256) Compliant with FIPS Publication 180-2
– 256 Fuse bits for crypto key and 64 Fuse bits for device configuration, including
JTAG disable and forced boot from the on-chip ROM
I/O
– Four 32-bit Parallel Input/Output Controllers
– 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os
– Input Change Interrupt Capability on Each I/O Line, optional Schmitt Trigger input
– Individually Programmable Open-drain, Pull-up and Pull-down Resistor,
Synchronous Output
– Packages: 217-ball BGA, pitch 0.8 mm, and 247-ball BGA, pitch 0.5 mm
•
AT91SAM
ARM-based
Embedded MPU
SAM9N12
SAM9CN11
SAM9CN12
•
•
•
•
11063G–ATARM–09-Oct-12
1. Description
The ARM926EJ-S based SAM9CN12 features the frequently requested combination of user
interface functionality and high data rate connectivity, including LCD Controller, resistive
touch-screen, multiple UARTs, SPI, I2C, full speed USB Host and Device and SDIO.
The SAM9CN12 supports the latest generation of LPDDR/DDR2 and NAND Flash memory
interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture
associated with 8 DMA channels, a distributed memory including a 32-Kbyte SRAM, sustains
the high bandwidth required by the processor and the high speed peripherals.
Embedded on SAM9CN12, on-chip hardware accelerators with DMA support, enable high-
speed data encryption and authentication of the transferred data or application. Supported
standards are up to 256-bit AES, and FIPS Publication 180-2 compliant SHA1 and SHA256. A
True Random Number Generator is embedded for key generation and exchange protocols.
There are fuse bits for crypto key (SAM9CN12), user configuration (SAM9N12 and
SAM9CN11) and device configuration (All). SAM9CN12 includes a Secured Boot ROM.
SAM9N12 and SAM9CN11 include a Standard Boot ROM.
The I/Os support 1.8V or 3.3V operation, which are independently configurable for the mem-
ory interface and peripheral I/Os. This feature completely eliminates the need for any external
level shifters. In addition it supports 0.8 ball pitch package for low cost PCB manufacturing.
The SAM9CN12 power management controller features efficient clock gating and a battery
backup section minimizing power consumption in active and standby modes.
There are several devices. The following table shows the embedded features.
Table 1-1.
Devices
Device
Standard Boot with BSC
Secured Boot
TRNG
AES
SHA
SAM9N12
X
-
X
-
-
SAM9CN11
X
-
X
X
X
SAM9CN12
-
X
X
X
X
2
SAM9N12/SAM9CN11/SAM9CN12
11063G–ATARM–09-Oct-12
3. Signal Description
Table 3-1
gives details on the signal names classified by peripheral.
Table 3-1.
Signal Name
Signal Description List
Function
Clocks, Oscillators and PLLs
Type
Active Level
XIN
XOUT
XIN32
XOUT32
VBG
PCK0 - PCK1
Main Oscillator Input
Main Oscillator Output
Slow Clock Oscillator Input
Slow Clock Oscillator Output
Bias Voltage Reference for USB
Programmable Clock Output
Shutdown, Wakeup Logic
Input
Output
Input
Output
Analog
Output
SHDN
WKUP
Shut-Down Control
Wake-Up Input
ICE and JTAG
Output
Input
TCK
TDI
TDO
TMS
JTAGSEL
RTCK
Test Clock
Test Data In
Test Data Out
Test Mode Select
JTAG Selection
Return Test Clock
Reset/Test
Input
Input
Output
Input
Input
Output
NRST
NTRST
BMS
Microcontroller Reset
Test Reset Signal
Boot Mode Select
Debug Unit - DBGU
I/O
Input
Input
Low
DRXD
DTXD
Debug Receive Data
Debug Transmit Data
Advanced Interrupt Controller - AIC
Input
Output
IRQ
FIQ
External Interrupt Input
Fast Interrupt Input
Input
Input
PIO Controller - PIOA - PIOB - PIOC - PIOD
PA0 - PA31
PB0 - PB18
PC0 - PC31
PD0 - PD21
Parallel IO Controller A
Parallel IO Controller B
Parallel IO Controller C
Parallel IO Controller D
I/O
I/O
I/O
I/O
4
SAM9N12/SAM9CN11/SAM9CN12
11063G–ATARM–09-Oct-12
SAM9N12/SAM9CN11/SAM9CN12
Table 3-1.
Signal Name
Signal Description List (Continued)
Function
External Bus Interface - EBI
Type
Active Level
D0 -D15
D16 -D31
A0 - A25
NWAIT
Data Bus
Data Bus
Address Bus
External Wait Signal
Static Memory Controller - SMC
I/O
I/O
Output
Input
Low
NCS0 - NCS5
NWR0 - NWR3
NRD
NWE
NBS0 - NBS3
Chip Select Lines
Write Signal
Read Signal
Write Enable
Byte Mask Signal
NAND Flash Support
Output
Output
Output
Output
Output
Low
Low
Low
Low
Low
NFD0-NFD15
NANDCS
NANDOE
NANDWE
NAND Flash I/O
NAND Flash Chip Select
NAND Flash Output Enable
NAND Flash Write Enable
DDR2/SDRAM/LPDDR Controller
I/O
Output
Output
Output
Low
Low
Low
SDCK,#SDCK
SDCKE
SDCS
BA[0..2]
SDWE
RAS - CAS
SDA10
DQS[0..1]
DQM[0..3]
DDR2/SDRAM differential clock
DDR2/SDRAM Clock Enable
DDR2/SDRAM Controller Chip Select
Bank Select
DDR2/SDRAM Write Enable
Row and Column Signal
SDRAM Address 10 Line
Data Strobe
Write Data Mask
Output
Output
Output
Output
Output
Output
Output
I/O
Output
High
Low
Low
Low
Low
High Speed Multimedia Card Interface - HSMCI
MCI_CK
MCI_CDA
MCI_DA0 -
MCI_DA7
Multimedia Card Clock
Multimedia Card Slot Command
Multimedia Card Slot Data
I/O
I/O
I/O
Universal Synchronous Asynchronous Receiver Transmitter- USARTx
SCKx
TXDx
RXDx
RTSx
CTSx
USARTx Serial Clock
USARTx Transmit Data
USARTx Receive Data
USARTx Request To Send
USARTx Clear To Send
I/O
Output
Input
Output
Input
5
11063G–ATARM–09-Oct-12
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