Features ..................................................................................................................................................................... 1
Clock Control and PLL......................................................................................................................................... 5
High-Speed (HS) Clock Data Recovery (CDR) ...................................................................................... ............. 5
USB Transceiver.................................................................................................................................................. 5
Full-Speed (FS) Clock Data Recovery (CDR) ..................................................................................................... 5
Line State Detect ................................................................................................................................................. 5
Pin Information ........................................................................................................................................................... 7
Control Interface Pins ................................................................................................................................... 9
USB Interface Pins ..................................................................................................................................... 10
Data Input/Output Pins (8-Bit) .................................................................................................................... 10
Data Input/Output Pins (16-Bit) .................................................................................................................. 10
Data Input Pins (Transmit) ......................................................................................................................... 11
Data Output Pins (Receive) ........................................................................................................................ 11
HS Functionality of the USS2X1A ............................................................................................................................ 13
Other Functions........................................................................................................................................................ 21
Assertion of Resume ......................................................................................................................................... 29
Detection of Resume ......................................................................................................................................... 30
USB 2.0 Test Mode Generation......................................................................................................................... 32
dc Characteristics .............................................................................................................................................. 33
ac Characteristics .............................................................................................................................................. 33
ac Timing ........................................................................................................................................................... 35
Ordering Information ................................................................................................................................................ 39
2
Agere Systems Inc.
Data Sheet, Rev. 3
October 2002
Agere Systems USB 2.0 UTMI
USS2X1A 8-Bit and USS2X1WA 16-Bit PHY
Table of Contents
(continued)
Figure
Page
Figure 1. USB 2.0 USS2X1A 8-Bit and USS2X1WA 16-Bit PHY Chips ...................................................................4
Table 14. Attach and Reset Timing Values ............................................................................................................31
Table 15. USB 2.0 Test Mode to USS2X1 Mapping ...............................................................................................32
Table 16. dc Characteristics ...................................................................................................................................33
Table 17. ac Characteristics ...................................................................................................................................33
Table 18. ac Timing (16-Bit) ...................................................................................................................................34
Table 19. ac Timing (8-Bit) .....................................................................................................................................35
Table 20. Timing Constraints for USS2X1 (8-Bit) ...................................................................................................36
Table 21. Timing Constraints for USS2X1 (8-Bit) ...................................................................................................37
Agere Systems Inc.
3
Agere Systems USB 2.0 UTMI
USS2X1A 8-Bit and USS2X1WA 16-Bit PHY Chips
Data Sheet, Rev. 3
October 2002
Functional Block Diagram
Figure 1 shows the functional block diagram of the USB 2.0 PHY chip. Each block is described below. It is assumed
that the control and data interface pins are externally connected to a logic block that performs the next layer of USB
processing, such as packet decoding. In this document, the external logic block that performs this function is referred
to as the SIE (serial interface engine).
USB 2.0 USS2X1A 8-bit AND USS2X1WA 16-bit PHY CHIP
RESETN
SUSPENDN
XI
XO
CLOCK
CONTROL
PLL
CLKOUT
RREF
TXVALID
TRANSMIT
LOGIC
TXREADY
BIT STUFF
NRZI ENCODE
DATA{15:0]*
DATA[7:0]*
VALIDH
†
USB
TRANSCEIVER
HS/FS
DP, DM
RECEIVE
LOGIC
OPMODE[1:0]
RXVALID
RXERROR
RXACTIVE
BIT UNSTUFF
NRZI DECODE
ELASTICITY
BUFFER
HS
CDR
TERMSELECT
FS
CDR
XCVRSELECT
LINESTATE[1:0]
LINE STATE
DETECT
5-9296(F).b R.02
†
* DATA[15:0] only exists on the 16-bit PHY chip, and DATA[7:0] only exists on the 8-bit PHY chip.
VALIDH only exists on the 16-bit PHY chip.
Figure 1. USB 2.0 USS2X1A 8-Bit and USS2X1WA 16-Bit PHY Chips
4
Agere Systems Inc.
Data Sheet, Rev. 3
October 2002
Agere Systems USB 2.0 UTMI
USS2X1A 8-Bit and USS2X1WA 16-Bit PHY Chips
filled to a threshold prior to enabling the remainder of
the downstream receive logic.
Overflow or underflow conditions detected in the elastic-
ity buffer are reported with the RXError signal.
Functional Block Diagram
(continued)
Clock Control and PLL
The clock control and PLL blocks generate the appropri-
ate internal clocks for the USS2X1(W)A and the CLK-
OUT output signal (60 MHz for the 8-Bit USS2X1A and
30 MHz for the 16-Bit USS2X1WA). An external 30 MHz
crystal must be connected to the XI and XO pins to pro-
vide a reference clock for these blocks. All data transfer
signals are synchronized with the CLKOUT output.
After the deassertion of SUSPENDN, the CLKOUT sig-
nal generated by the USS2X1(W)A will behave as fol-
lows:
s
Transmit Logic
The transmit logic block is responsible for accepting
8-/16-bit parallel data from the parallel application bus
(i.e., the SIE) interface upon command and serializing it
for transmission over the USB 2.0 interface. This mod-
ule also includes logic for bit stuffing, NRZI encoding,
SYNC field, and
EOP generation. This block is used for
both HS and FS transmit.
Produce the first CLKOUT transition no later than
5.6 ms after the deassertion of SUSPENDN.
The CLKOUT signal frequency error will be less than
±10%.
The CLKOUT signal will fully meet the required accu-
racy of ±500 ppm, no later than 1.4 ms after the first
transition of CLKOUT.
s
Receive Logic
The receive logic block is responsible for deserializing
received data recovered by the HS CDR or FS CDR,
and providing 8-/16-bit parallel data to the application’s
parallel interface with the SIE. This module also
includes logic for bit unstuffing, NRZI decoding, SYNC
field and EOP field detection, and stripping. This block
is used for both HS and FS receive.
s
In HS mode, there is one CLKOUT cycle per byte time
for the 8-Bit USS2X1A. In FS mode for the USS2X1A,
there are 5 CLKOUT cycles per FS bit time and 40 CLK-
OUT cycles per FS byte time. If a received byte contains
a stuffed bit, then the byte boundary can be stretched to
45 CLKOUT cycles and two stuffed bits would result in a
50 CLKOUT delay between bytes.
The frequency of CLKOUT does not change when the
USS2X1(W)A is switched between HS and FS modes.
USB Transceiver
The USB transceiver is capable of transmitting and
receiving at the HS or FS bit rates and edge rates, as
controlled by the XCVRSELECT input. The transceiver
also detects line inactivity (squelch) and the line state
in both HS and FS modes. All termination resistors
required by the USB 2.0 specification are located inter-
nally, and are controlled by the TERMSELECT input.
The XCVRSELECT signal determines whether the HS
or FS timing relationship is applied to the data and con-
trol signals.
High-Speed (HS) Clock Data Recovery (CDR)
The clock data recovery (CDR) block recovers the serial
480 Mbits/s data received by the transceiver when in
HS mode, as indicated by the XCVRSELECT input.
Full-Speed (FS) Clock Data Recovery (CDR)
The full-speed (FS) clock data recovery (CDR) block
recovers the serial 12 Mbits/s data received by the
transceiver when in FS mode, as indicated by the
XCVRSELECT input. This block also accounts for any
differences between the local clock frequency, i.e.,
crystal oscillator, and the rate at which FS data is
received.
Elasticity Buffer
As defined in the USB 2.0 specification, the elasticity
buffer manages any differences between the local clock
frequency (derived from the crystal oscillator) and the
rate at which HS data is received.
The USB specification defines a maximum clock error of
±500
ppm. When the error is calculated over the maxi-
mum packet size and when the other system timing
margin is taken into consideration, up to
±12
bits of drift
can occur. At the start of a packet, the elasticity buffer is
Line State Detect
Reports the logic state received from either the HS or
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