MK1707
Low EMI Clock Generator
Description
The MK1707 generates a low EMI output clock from a
clock input. The part is designed to dither the LCD
interface clock for flat panel graphics controllers. The
device uses ICS’ proprietary mix of analog and digital
Phase Locked Loop (PLL) technology to spread the
frequency spectrum of the output, thereby reducing the
frequency amplitude peaks by several dB.
The MK1707 offers both centered and down spread
from a high speed clock input. Refer to the
MK1714-01/02 for a crystal input and the widest
selection of input frequencies and multipliers.
ICS offers many other clocks for computers and
computer peripherals. Consult us when you need to
remove crystals and oscillators from your board.
Features
•
•
•
•
•
•
•
Packaged in 8-pin SOIC
Available in Pb-free package
Industrial temperature range available
Provides a spread spectrum output clock
Supports ATI’s flat panel controllers
Guaranteed to +85°C operation
Accepts a clock input, provides same frequency
dithered output
•
Good for all VGA modes from 80 to 167 MHz
•
Peak reduction by 7dB - 14dB typical on 3rd - 19th
odd harmonics
•
•
•
•
Low EMI feature can be disabled
Includes Power-down
Operating voltage of 3.3 V or 5 V
Advanced, low-power CMOS process
Block Diagram
VDD
S1:0
Spread Direction
Low EMI Enable
2
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
Input
Buffer
Clock Out
ICLK
GND
MDS 1707 G
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 032204
tel (408) 297-1201
●
www.icst.com
MK1707
Low EMI Clock Generator
Pin Assignment
Spread Direction and Percentage
Select Table
8
7
6
5
SD
S1
S0
LEE
SD
Pin 8
S1
Pin 7
S0
Pin 6
0
M
1
0
M
1
0
M
1
0
M
1
0
M
1
0
M
1
Spread
Direction
Down
Down
Down
Down Center
Down
Down Center
Down Center
Down
Power Down
Center
Center
Center
Center
Center
Center
Test
Center
Power Down
Spread
Percentage (%)
0.6
0.8
1.25
+0.5, -1.5
2
+0.5, -2.5
+0.5, -3
5
-
±0.35
±0.5
±0.7
±0.8
±1.1
±1.4
Test
±2.5
-
ICLK
VDD
GND
CLK
1
2
3
4
8 pin (150 mil) SOIC
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
M
M
M
1
1
1
0
0
0
M
M
M
1
1
1
0 = connect to GND
M = unconnected (floating)
1 = connect directly to VDD
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
ICLK
VDD
GND
CLK
LEE
S0
S1
SD
Input
Power
Power
Output
Input
Input
Input
Input
Connect to graphics input clock.
Connect to +3.3 V.
Connect to ground.
Spread spectrum clock output per table above.
Low EMI enable. Turns on spread spectrum when high. Internal pull-up resistor.
Function select 0 input. Selects spread amount and direction per table above.
Internal mid-level.
Function select 1input. Selects spread amount and direction per table above.
Internal mid-level.
Spread direction select input. Selects the direction of spread per table above.
Internal pull-up resistor.
MDS 1707 G
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 032204
tel (408) 297-1201
●
www.icst.com
MK1707
Low EMI Clock Generator
External Components
The MK1707 requires a minimum number of external
components for proper operation.
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI, the 33
Ω
series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the MK1707. This includes signal traces just
underneath the device, or on layers adjacent to the
ground plane layer used by the device.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between VDD and GND on pins 2 and 3, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output and the
load is over 1 inch, series termination should be used.
To series terminate a 50
Ω
trace (a commonly used
trace impedance), place a 33
Ω
resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
20
Ω
.
Powerup Considerations
To insure proper operation of the spread spectrum
generation circuit, some precautions must be taken
while utilizing the MK1707.
1. An input signal should not be applied to ICLK until
VDD is stable (within 10% of its final value). This
requirement can easily be met by operating the
MK1707 and then ICLK source from the same power
supply.
2. LEE should not be enabled (taken high) until after
the power supplies and input clock are stable. This
requirement can be met by direct control of LEE by
system logic - for example, a “power good” signal.
Another solution is to leave LEE unconnected to
anything but a 0.01
µ
F capacitor to ground. The internal
pullup resistor on LEE will charge the capacitor and
provide approximately a 700
µ
s delay until spread
spectrum is enabled.
3. If the input frequency is changed during operation,
disable spread spectrum until the input clock stabilizes
at the new frequency.
Tri-level Select Pin Operation
The S1, S0 select pins are tri-level, meaning they have
three separate states to make the selections shown in
the table on page 2. To select the M (mid) level, the
connection to these pins must be eliminated by either
floating them originally, or tri-stating the GPIO pins
which drive the select pins.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
MDS 1707 G
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 032204
tel (408) 297-1201
●
www.icst.com
MK1707
Low EMI Clock Generator
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1707. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature, Commercial
Ambient Operating Temperature, Industrial
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
0 to +85
°
C
-40 to +85
°
C
-65 to +150
°
C
125
°
C
260
°
C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
0
+3.135
Typ.
Max.
+85
+5.5
Units
°
C
V
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V
, Ambient Temperature 0 to +85
°
C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
IDD
IDD
IDDPD
Conditions
No load, at 3.3 V
No load, at 5 V
S0=S1=SD=1
ICLK
ICLK
S1, S0
other inputs
S0, S1, SD, LEE pins
CMOS, I
OH
= -4 mA
I
OH
= -12 mA
I
OL
= -12 mA
S0, S1, SD, LEE pins
Min.
3.135
Typ.
20
31
60
Max.
5.5
Units
V
mA
mA
µ
A
Input High Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
V
IH
V
IL
V
IH
V
IH
V
IL
V
OH
V
OH
V
OL
C
IN
(VDD/2) + 1
VDD-0.5
2
VDD/2
VDD/2
(VDD/2) - 1
V
V
V
V
0.5
V
V
V
0.4
V
pF
VDD-0.4
2.4
5
MDS 1707 G
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 032204
tel (408) 297-1201
●
www.icst.com
MK1707
Low EMI Clock Generator
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V
, Ambient Temperature 0 to +85
°
C
Parameter
Input/Output Clock Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Output Rise Time
Output Fall Time
Modualtion Frequency
EMI Peak Frequency Reduction
Symbol
Conditions
Time above VDD/2
Time above 1.5 V
Min.
80
20
40
Typ.
Max. Units
167
80
MHz
%
%
ns
ns
41
kHz
dB
50
1.5
1.5
60
t
OR
t
OF
0.8 to 2.0 V
2.0 to 0.8 V
19
3rd - 19th odd
harmonics
7 to 14
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
150
140
120
40
Max. Units
°
C/W
°
C/W
°
C/W
°
C/W
Thermal Resistance Junction to Case
MDS 1707 G
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 032204
tel (408) 297-1201
●
www.icst.com
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
