NCV8843
1.5 A, 340 kHz, Buck
Regulator with
Synchronization Capability
The NCV8843 is a 1.5 A buck regulator IC operating at a
fixed−frequency of 340 kHz. The device uses the V
2
t
control
architecture to provide unmatched transient response, the best overall
regulation and the simplest loop compensation for today’s high−speed
logic. The NCV8843 accommodates input voltages from 4.0 V to 40 V
and contains synchronization circuitry.
The on−chip NPN transistor is capable of providing a minimum of
1.5 A of output current, and is biased by an external “boost” capacitor
to ensure saturation, thus minimizing on−chip power dissipation.
Protection circuitry includes thermal shutdown, cycle−by−cycle
current limiting and frequency foldback.
Features
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MARKING
DIAGRAMS
16
16
1
1
1
18
1
DFN18
MN SUFFIX
CASE 505
NCV8843
AWLYYWW
G
G
18
SO−16W EP
PW SUFFIX
CASE 751AG
NCV8843
AWLYYWWG
•
V
2
Architecture Provides Ultra−Fast Transient Response, Improved
•
•
•
•
•
•
•
•
•
•
•
•
Regulation and Simplified Design
Wide Operating Range: 4 V to 40 V
2.0% Error Amp Reference Voltage Tolerance
Switch Frequency Decrease of 4:1 in Short Circuit Conditions
Reduces Short Circuit Power Dissipation
BOOST Lead Allows “Bootstrapped” Operation to Maximize
Efficiency
Sync Function for Parallel Supply Operation or Noise Minimization
Shutdown Lead Provides Power−Down Option
1.0
mA
Quiescent Current During Power−Down
Thermal Shutdown
Soft−Start
Exposed Pad Packages for Enhanced Thermal Characteristics
NCV Prefix for Automotive and Other Applications Requiring Site
and Change Control
These are Pb−Free Devices
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
A
WL, L
YY, Y
WW, W
E
G or
G
V8843
ALYWE
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Automotive Grade
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
©
Semiconductor Components Industries, LLC, 2010
May, 2010
−
Rev. 10
1
Publication Order Number:
NCV8843/D
NCV8843
R6
100k
D1
L1
18
mH
Vout (3.3 V)
R3
162
C1
0.1
mF
U1
EPAD
Vsw
SHDNB
NC
NC
NC
NC
SYNC
GND
Vin
BOOST
NC
NC
NC
NC
Vc
Vfb
Vin (7 V to 16 V)
C5
0.1
mF
+ C2
330
mF
C4
0.1
mF
D2
C3
100
mF
+
NCV8843
R2
100
SHDNB
SYNC
Figure 1. Application Diagram, 7.0 V
−
16 V to 3.3 V @ 1.0 A Converter
MAXIMUM RATINGS*
Rating
Peak Transient Voltage (31 V Load Dump @ V
IN
= 14 V)
Operating Junction Temperature Range, T
J
Lead Temperature Soldering:
Storage Temperature Range, T
S
ESD
(Human Body Model)
(Machine Model)
(Charge Device Model)
SO−16W EPAD Junction−to−Case, R
qJC
SO−16W EPAD Junction−to−Ambient, R
qJA
(Note 3)
DFN18 Junction−to−Ambient, R
qJA
(Note 3)
SO−8 Junction−to−Ambient, R
qJA
(Note 4)
Reflow: (Note 1)
Value
45
−40
to 150
260 peak
(Note 2)
−65
to +150
2.0
200
>1.0
16
35
38
100
Unit
V
°C
°C
°C
kV
V
kV
°C/W
°C/W
°C/W
°C/W
Package Thermal Resistance
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
*The maximum package power dissipation must be observed.
1. 60 second maximum above 183°C.
2.
−5°C/0°C
allowable conditions.
3. 4 layer board, 1 oz copper outer layers, 0.5 oz copper inner layers, 600 sq mm copper area.
4. 1 in
2
, 1 oz copper area used for heatsinking.
MAXIMUM RATINGS
(Voltages are with respect to GND)
Pin Name
V
IN
(DC)*
BOOST
V
SW
V
C
SHDNB
SYNC
V
FB
*See table above for load dump.
V
Max
40 V
40 V
40 V
7.0 V
7.0 V
7.0 V
7.0 V
V
MIN
−0.3
V
−0.3
V
−0.6
V/−1.0 V, t < 50 ns
−0.3
V
−0.3
V
−0.3
V
−0.3
V
I
SOURCE
N/A
N/A
4.0 A
1.0 mA
1.0 mA
1.0 mA
1.0 mA
I
SINK
4.0 A
100 mA
10 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
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NCV8843
PACKAGE PIN DESCRIPTION
SO−8
1
2
3
SO−16W
EPAD
15
16
1
DFN−18
1
2−4
5−7
PIN
SYMBOL
BOOST
V
IN
V
SW
FUNCTION
The BOOST pin provides additional drive voltage to the on−chip NPN power tran-
sistor. The resulting decrease in switch on voltage increases efficiency.
This pin is the main power input to the IC.
This is the connection to the emitter of the on−chip NPN power transistor and
serves as the switch output to the inductor. This pin may be subjected to negative
voltages during switch off−time. A catch diode is required to clamp the pin voltage
in normal operation. This node can stand
−1.0
V for less than 50 ns during switch
node flyback.
The shutdown pin is active low and TTL compatible. The IC goes into sleep mode,
drawing less than 1.0
mA
when the pin voltage is pulled below 1.0 V.
This pin should be pulled up to V
CC
with resistor.
External synchronization single input, with 60k internal pull−down resistor. If not
used, leave unconnected or connect to GND.
Power return connection for the IC.
The FB pin provides input to the inverting input of the error amplifier. If V
FB
is lower
than 0.29 V, the oscillator frequency is divided by four, and current limit folds back
to about 1 A. These features protect the IC under severe overcurrent or short cir-
cuit conditions.
The V
C
pin provides a connection point to the output of the error amplifier and
input to the PWM comparator. Driving of this pin should be avoided because on−
chip test circuitry becomes active whenever current exceeding 0.5 mA is forced
into the IC.
No Connection
Exposed die attach pad. Internally connected to GND. External connection to GND
is optional.
4
2
8
SHDNB
5
6
7
7
8
9
10
13
16
SYNC
GND
V
FB
8
10
17
V
C
−
−
3
−
6,
11
−
14
EPAD
9, 11, 12,
14, 15, 18
EPAD
NC
−
PIN CONNECTIONS
1
V
SW
1
BOOST
V
IN
V
SW
SHDNB
8
SHDNB
V
C
V
FB
GND
SYNC
NC
NC
NC
NC
SYNC
GND
16
V
IN
BOOST
NC
NC
NC
NC
V
C
V
FB
BOOST
V
IN
V
IN
V
IN
V
SW
V
SW
V
SW
SHDNB
NC
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
NC
V
C
V
FB
NC
NC
GND
NC
NC
SYNC
SO−8
DFN18
SO−16W EPAD
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3
NCV8843
ELECTRICAL CHARACTERISTICS
(−40°C < T
J
< 150°C, 4.5 V< V
IN
< 40 V; unless otherwise specified.)
Characteristic
Oscillator
Operating Frequency
Frequency Line Regulation
Maximum Duty Cycle
V
FB
Frequency Foldback Threshold
PWM Comparator
Slope Compensation Voltage
Minimum Output Pulse Width
Power Switch
Current Limit
Foldback Current
Saturation Voltage
Current Limit Delay
Error Amplifier
Internal Reference Voltage
Reference PSRR
FB Input Bias Current
Output Source Current
Output Sink Current
Output High Voltage
Output Low Voltage
Unity Gain Bandwidth
Open Loop Amplifier Gain
Amplifier Transconductance
Sync
Sync Frequency Range
Sync Pin Bias Current
Sync Threshold Voltage
Shutdown
Shutdown Threshold Voltage
SHDNB Input Current
Thermal Shutdown
Overtemperature Trip Point
Thermal Shutdown Hysteresis
(Note 5)
(Note 5)
175
−
185
42
195
−
°C
°C
V
in
= 5.0 V (Note 5)
−
1.0
−
1.3
4.0
1.6
−
V
mA
V
SYNC
= 5.0 V
−
−
377
−
0.9
−
360
1.5
710
485
1.9
kHz
mA
V
(Note 5)
−
V
C
= 1.270 V, V
FB
= 1.0 V
V
C
= 1.270 V, V
FB
= 2.0 V
V
FB
= 1.0 V
V
FB
= 2.0 V
(Note 5)
(Note 5)
(Note 5)
−
1.244
−
−
15
15
1.39
5.0
−
−
−
1.270
40
0.02
25
25
1.46
20
500
70
6.4
1.296
−
0.1
35
35
1.53
60
−
−
−
V
dB
mA
mA
mA
V
mV
kHz
dB
mA/V
V
FB
> 0.36 V
V
FB
< 0.29 V
I
OUT
= 1.5 A, V
BOOST
= V
IN
+ 2.5 V
(Note 5)
1.6
0.9
0.4
−
2.3
1.5
0.7
120
3.0
2.1
1.0
160
A
A
V
ns
Fix V
FB,
DV
C
/DT
ON
V
FB
to V
SW
5.0
−
9.0
100
17
200
mV/ms
ns
−
−
−
−
306
−
85
0.29
340
0.05
90
0.32
374
0.15
95
0.36
kHz
%/V
%
V
Test Conditions
Min
Typ
Max
Unit
5. Guaranteed by design, not 100% tested in production.
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4
NCV8843
ELECTRICAL CHARACTERISTICS (continued)
(−40°C < T
J
< 150°C, 4.5 V< V
IN
< 40 V; unless otherwise specified.)
Characteristic
General
Quiescent Current
Shutdown Quiescent Current
Boost Operating Current
Minimum Boost Voltage
Startup Voltage
Minimum Output Current
6. Guaranteed by design, not 100% tested in production.
I
SW
= 0 A
V
SHDNB
= 0 V,
−40°C
< T
J
< 125°C
V
BOOST
−
V
SW
= 2.5 V
(Note 6)
−
−
−
−
6.0
−
3.0
−
4.0
1.0
15
−
3.5
7.0
7.5
5.0
40
2.5
4.0
12
mA
mA
mA/A
V
V
mA
Test Conditions
Min
Typ
Max
Unit
SHDNB
V
IN
SYNC
2.9 V LDO
Voltage
Regulator
Internal rail
Shutdown
Comparator
+
−
+
1.2 V
−
4
mA
Artificial
Ramp
Oscillator
Thermal
Shutdown
BOOST
S
R
Q
Output
Driver
V
SW
∑
+
−
SHDNB
1.46 V
PWM Com-
parator
−
V
FB
+
−
−
+
1.27 V
Error
Amplifier
+
0.32 V
−
+
Frequency
and Current
Limit Foldback
I
FOLDBACK
Current
Limit Com-
parator
I
REF
+
5
−
GND
V
C
Figure 2. Block Diagram
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