NCP1379
Quasi-Resonant
Current-Mode Controller for
High-Power Universal
Off-line Supplies
The NCP1379 hosts a high−performance circuitry aimed to
powering quasi−resonant converters. Capitalizing on a proprietary
valley−lockout system, the controller shifts gears and reduces the
switching frequency as the power loading becomes lighter. This
results in a stable operation despite switching events always occurring
in the drain−source valley. This system works down to the 4
th
valley
and toggles to a variable frequency mode beyond, ensuring an
excellent standby power performance.
The controller includes an Over Power Protection circuit which
clamps the delivered power at high−line. Safety−wise, a fixed internal
timer relies on the feedback voltage to detect a fault. Once the timer
elapses, the controller stops and enters auto−recovery mode, ensuring
a low duty−cycle burst operation. To further improve the safety of the
power supply, the NCP1379 features a pin to implement a combined
brown−out/overvoltage protection.
Particularly well suited for TVs power supply applications, the
controller features a low startup voltage allowing the use of an
auxiliary power supply to power the device.
Features
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QUASI−RESONANT PWM
CONTROLLER FOR HIGH
POWER AC−DC WALL AD-
APTERS
MARKING
DIAGRAMS
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
1379
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
1379
ALYW
G
•
Quasi−Resonant Peak Current−Mode Control Operation
•
Valley Switching Operation with Valley−Lockout for Noise−Immune
•
•
•
•
•
•
•
•
•
•
•
•
Operation
Frequency Foldback at Light Load to Improve the Light Load
Efficiency
Adjustable Over Power Protection
Auto−Recovery Output Short−Circuit Protection
Fixed Internal 80 ms Timer for Short−Circuit Protection
Combined Overvoltage Protection and Brown−out
+500 mA /
−800
mA Peak Current Source/Sink Capability
Internal Temperature Shutdown
Direct Optocoupler Connection
Low V
CC(on)
Allowing to Use a Standby Power Supply to Power the
Device
Extremely Low No−Load Standby Power
SO8 Package
These Devices are Pb−Free and are RoHS Compliant
PIN CONNECTIONS
ZCD 1
FB 2
CS 3
GND 4
8 CT
7 FAULT
6 VCC
5 DRV
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
Typical Applications
•
High Power ac−dc Converters for TVs, Set−Top Boxes etc.
•
Offline Adapters for Notebooks
©
Semiconductor Components Industries, LLC, 2011
July, 2011
−
Rev. 2
1
Publication Order Number:
NCP1379/D
NCP1379
TYPICAL APPLICATION EXAMPLE
HV
−bulk
.
.
NCP 1 3 7 9
1
2
3
4
.
Vout
GND
8
7
6
5
VCC
ZCD / OPP
Figure 1. Typical Application Schematic
GND
PIN FUNCTION DESCRIPTION
Pin N5
1
Pin Name
ZCD
Function
Zero Crossing Detection
Adjust the over power protection
Pin Description
Connected to the auxiliary winding, this pin detects the core reset
event.
Also, injecting a negative voltage smaller than 0.3 V on this pin will
perform over power protection.
Hooking an optocoupler collector to this pin will allow regulation.
This pin monitors the primary peak.
The controller ground
The driver’s output to an external MOSFET
This pin is connected to an external auxiliary voltage.
This pin observes the HV rail and protects the circuit in case of low
main conditions. It also offers a way to latch the circuit in case of over
voltage event.
A capacitor connected to this pin acts as the timing capacitor in fold-
back mode.
2
3
4
5
6
7
FB
CS
GND
DRV
V
CC
Fault
Feedback pin
Current sense
−
Driver output
Supplies the controller
Overvoltage protection
Brown−out
Timing capacitor
8
C
T
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2
NCP1379
INTERNAL CIRCUIT ARCHITECTURE
VDD
BO r e se t
latch
VDD
Rpullup
FB
LOGIC BLOCK
VDD
Vcc
V
CC
management
fa ul t
gr a nd
reset
V CCstop
V cc aux
VDD
ICt
Ct
C t s e tpoint
+
−
R
Q
Q
DRV
gr a nd
reset
clamp
DRV
ga te
ZC D
Ct
Discharge
+
10 V
ESD
DRV
−
Vth
3
ms
blanking
S
Q
Q
de ma g
S
GN D
CsS top
La ux
SS end
40
ms
Time Out
The 40
ms
Time Out is active
only during s oft−s ta r t
SS end
I
peak(VCO)
= 17.5 % V
ILIMIT
CS
LEB 1
Rsense
OPP
+
Soft-start
−
+
−
5
ms
Time Out
PW Mreset
R
TIMER
Reset
Up
Down
IpFlag
PW Mreset
/4
gr a nd
reset
noi s e de l a y
+
−
VOVP
VCC HV
I pFl a g
VDD
IBO
noise delay
VBO
+
−
BO r e se t
Rclamp
Vclamp
OVP/BO
VILIMIT
LEB 2
LE B 2 is shorter than LE B 1
Soft-start end ? then 1
else 0
Cs S top
SS end
+
−
VCS(stop )
Figure 2. Internal Circuit Architecture
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3
NCP1379
MAXIMUM RATINGS TABLE(S)
Symbol
V
CC(MAX)
I
CC(MAX)
V
DRV(MAX)
I
DRV(MAX)
V
MAX
I
MAX
I
ZCD(MAX)
R
qJA
T
J(MAX)
Rating
Maximum Power Supply voltage, VCC pin, continuous voltage
Maximum current for VCC pin
Maximum driver pin voltage, DRV pin, continuous voltage
Maximum current for DRV pin
Maximum voltage on low power pins (except pins DRV and V
CC
)
Current range for low power pins (except pins ZCD, DRV and V
CC
)
Maximum current for ZCD pin
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
ESD Capability, Human Body Model (HBM) model (Note 1)
ESD Capability, CDM model (Note 1)
Value
−0.3
to 28
$30
−0.3
to 20
$1000
−0.3
to 10
$10
+3 /
−2
120
150
−40
to +125
−60
to +150
4
2
Unit
V
mA
V
mA
V
mA
mA
°C/W
°C
°C
°C
kV
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model 4000 V per JEDEC Standard JESD22,
Method A114E. Charged Device Model 2000 V per JEDEC Standard JESD22−C101D
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
V
CS
= 0 V, V
fault
= 1.5 V, C
T
= 680 pF) For min/max values T
J
=
−40°C
to +125°C, Max T
J
= 150°C, V
CC
= 12 V)
Symbol
Parameter
Conditions
Min
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: For typical values T
J
= 25°C, V
CC
= 12 V, V
ZCD
= 0 V, V
FB
= 3 V,
Typ
Max
Unit
SUPPLY SECTION
−
STARTUP AND SUPPLY CIRCUITS
V
CC(on)
V
CC(off)
V
CC(hyst)
V
CC(reset)
t
VCC(off)
t
VCC(reset)
I
CC(start)
Supply Voltage
Startup Threshold
Minimum Operating Voltage
Hysteresis V
CC(on)
−
V
CC(off)
Internal logic reset
V
CC(off)
noise filter
V
CC(reset)
noise filter
Startup current
Supply Current
Device Disabled/Fault (Note 3)
Device Enabled/No output load on pin 5
Device Switching (F
sw
= 65 kHz)
Device Switching (F
sw
around 12 kHz)
Current Sense Voltage Threshold
Leading Edge Blanking Duration for V
ILIM
Input Bias Current (Note 3)
Propagation Delay
Percentage of maximum peak current level at which
VCO takes over (Note 4)
FB pin open
V
CC
= V
CC(on)
−
0.5 V
V
CC
> V
CC(off)
F
sw
= 10 kHz
C
DRV
= 1 nF, F
sw
= 65 kHz
C
DRV
= 1 nF, V
FB
= 1.25 V
V
FB
= 4 V, V
CS
increasing
Minimum on time minus
t
ILIM
DRV high
V
CS
> V
ILIM
to DRV
turn−off
V
FB
= 0.4 V, V
CS
increasing
V
CC
increasing
V
CC
decreasing
V
CC
decreasing
10.5
8.3
2.0
6
−
−
−
11.4
9.0
2.4
7
5
20
0.7
12.3
9.4
−
8
−
−
1.2
V
ms
ms
mA
mA
I
CC1
I
CC2
I
CC3A
I
CC3B
V
ILIM
t
LEB
I
bias
t
ILIM
I
peak(VCO)
3.
4.
5.
6.
−
−
−
−
1.7
1.7
2.65
2.0
2.0
2.0
3.00
−
CURRENT COMPARATOR
−
CURRENT SENSE
0.76
210
−2
−
15.4
0.80
275
−
125
17.5
0.84
330
2
175
19.6
V
ns
mA
ns
%
Guaranteed by design
The peak current setpoint goes down as the load decreases. It is frozen below I
peak(VCO)
(I
peak
= cst)
If negative voltage in excess to
−300
mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear
Minimum value for T
J
= 125°C
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4
NCP1379
ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: For typical values T
J
= 25°C, V
CC
= 12 V, V
ZCD
= 0 V, V
FB
= 3 V,
V
CS
= 0 V, V
fault
= 1.5 V, C
T
= 680 pF) For min/max values T
J
=
−40°C
to +125°C, Max T
J
= 150°C, V
CC
= 12 V)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
CURRENT COMPARATOR
−
CURRENT SENSE
V
OPP(MAX)
V
CS(stop)
t
BCS
Setpoint decrease for V
ZCD
=
−300
mV (Note 5)
Threshold for immediate fault protection activation
Leading Edge Blanking Duration for V
CS(stop)
Drive Resistance
DRV Sink
DRV Source
Drive current capability
DRV Sink
DRV Source
Rise Time (10 % to 90 %)
Fall Time (90 % to 10 %)
DRV Low Voltage
DRV High Voltage (Note 6)
V
ZCD
=
−300
mV, V
FB
=
4 V, V
CS
increasing
35.0
1.125
−
37.5
1.200
120
40.0
1.275
−
%
V
ns
DRIVE OUTPUT
−
GATE DRIVE
R
SNK
R
SRC
I
SNK
I
SRC
t
r
t
f
V
DRV(low)
V
DRV(high)
V
DRV
= 10 V
V
DRV
= 2 V
V
DRV
= 10 V
V
DRV
= 2 V
C
DRV
= 1 nF, V
DRV
from 0
to 12 V
C
DRV
= 1 nF, V
DRV
from 0
to 12 V
V
CC
= V
CC(off)
+ 0.2 V
C
DRV
= 1 nF, R
DRV
=33 kW
V
CC
= V
CC(MAX)
C
DRV
= 1 nF
−
−
−
−
−
−
8.4
10.5
12.5
20
800
500
40
25
9.1
13.0
−
−
−
−
75
60
−
15.5
W
mA
ns
ns
V
V
DEMAGNETIZATION INPUT
−
ZERO VOLTAGE DETECTION CIRCUIT
V
ZCD(TH)
V
ZCD(HYS)
V
CH
V
CL
t
DEM
C
PAR
t
BLANK
t
outSS
t
out
R
ZCD(pdown)
V
CT(MAX)
I
CT
V
CT(MIN)
C
T
R
FB(pullup)
I
ratio
V
FB(TH)
3.
4.
5.
6.
ZCD threshold voltage
ZCD hysteresis
Input clamp voltage
High state
Low state
Propagation Delay
Internal input capacitance
Blanking delay after on−time
Timeout after last demag transition
Pulldown resistor (Note 3)
During soft−start
After the end of soft−start
V
ZCD
decreasing
V
ZCD
increasing
I
pin1
= 3.0 mA
I
pin1
=
−2.0
mA
V
ZCD
decreasing from 4 V
to
−0.3
V
35
15
8
−0.9
−
−
2.30
28
5.0
140
55
35
10
−0.7
150
10
3.15
41
5.9
320
90
55
12
−0.3
250
−
4.00
54
6.7
700
mV
mV
V
ns
pF
ms
ms
kW
TIMING CAPACITOR
−
TIMING CAPACITOR
Maximum voltage on C
T
pin
Source current
Minimum voltage on C
T
pin, discharge switch
activated
Recommended timing capacitor value
V
FB
< V
FB(TH)
V
CT
= 0 V
5.15
18
−
5.40
20
−
220
5.65
22
90
V
mA
mV
pF
FEEDBACK SECTION
−
FEEDBACK
Internal pullup resistor
Pin FB to current setpoint division ratio
FB pin threshold under which C
T
is clamped to
V
CT(MAX)
15
3.8
0.26
18
4.0
0.30
22
4.2
0.34
V
kW
Guaranteed by design
The peak current setpoint goes down as the load decreases. It is frozen below I
peak(VCO)
(I
peak
= cst)
If negative voltage in excess to
−300
mV is applied to ZCD pin, the current setpoint decrease is no longer guaranteed to be linear
Minimum value for T
J
= 125°C
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