NCP1253
Current-Mode PWM
Controller for Off-line
Power Supplies
The NCP1253 is a highly integrated PWM controller capable of
delivering a rugged and high performance offline power supply in a
tiny TSOP−6 package. With a supply range up to 28 V, the controller
hosts a jittered 65 kHz or 100 kHz switching circuitry operated in peak
current mode control. When the power on the secondary side starts to
decrease, the controller automatically folds back its switching
frequency down to a minimum level of 26 kHz. As the power further
goes down, the part enters skip cycle while limiting the peak current.
To avoid sub harmonic oscillations in CCM operation, adjustable
slope compensation is available via the series inclusion of a simple
resistor in the current sense signal.
Besides the auto−recovery timer−based short−circuit protection, an
Over Voltage Protection on the V
CC
pin protects the whole circuitry in
case of optocoupler destruction or adverse open loop operation.
Features
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1
TSOP−6
CASE 318G
STYLE 13
MARKING DIAGRAM
•
Fixed−Frequency 65 kHz or 100 kHz Current−Mode Control
•
•
•
•
•
•
•
•
•
53xAYWG
G
1
53
x
A
Y
W
G
= Specific Device Code
= A, 2, C, or D
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Operation
Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load
Conditions
Adjustable Ramp Compensation
Internally Fixed 4 ms soft−start
Timer−based Auto−Recovery or Latched Short−Circuit Protection
Frequency Jittering in Normal and Frequency Foldback Modes
Latched OVP on V
CC
Up to 28 V V
CC
Operation
Extremely Low No−load Standby Power
These are Pb−Free Devices
(Note: Microdot may be in either location)
PIN CONNECTIONS
GND
FB
NC
1
2
3
(Top View)
6
5
4
DRV
V
CC
CS
Typical Applications
•
Ac−dc Converters for TVs, Set−top Boxes and Printers
•
Offline Adapters for Notebooks and Netbooks
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2012
January, 2012
−
Rev. 0
1
Publication Order Number:
NCP1253/D
NCP1253
Vbulk
.
.
Vout
.
NCP1253
1
2
3
6
5
4
ramp
comp.
Figure 1. Typical Application Schematic
PIN FUNCTION DESCRIPTION
Pin No.
1
2
3
4
5
Pin Name
GND
FB
NC
CS
V
CC
Function
−
Feedback pin
Non−connected pin
Current sense + ramp compensation
Supplies the controller – protects the IC
The controller ground.
Hooking an optocoupler collector to this pin will allow
regulation.
The pin is electrically inert and can be grounded if necessary
This pin monitors the primary peak current but also offers a
means to introduce slope compensation.
This pin is connected to an external auxiliary voltage. An OVP
comparator monitors this pin and offers a means to latch the
converter in fault conditions.
The driver’s output to an external MOSFET gate.
Description
6
DRV
Driver output
OPTIONS
Controller
NCP1253ASN65T1G
NCP1253BSN65T1G
NCP1253ASN100T1G
NCP1253BSN100T1G
Frequency
65 kHz
65 kHz
100 kHz
100 kHz
OCP Latched
Yes
No
Yes
No
OCP Auto−Recovery
No
Yes
No
Yes
ORDERING INFORMATION
Package
Marking
53A
532
53C
53D
OCP
Protection
Latch
Auto
Recovery
Latch
Auto
Recovery
Switching
Frequency
(kHz)
65
65
100
100
TSOP−6
(Pb−Free)
3000 / Tape & Reel
Device
NCP1253ASN65T1G
NCP1253BSN65T1G
NCP1253ASN100T1G
NCP1253BSN100T1G
Package
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NCP1253
IpFlag
BO
Vcc logic
management
and fault timer
vdd
UVLO
20us time
constant
power
on reset
S
Q
Q
vdd
VOVP
Rlim
Vcc
R
Power on
reset
Frequency
modulation
65 kHz
100 kHz
clock
Clamp
S
Q
Q
R
Frequency
foldback
Vfold
Drv
Vskip
Rramp
VDD
RFB
4 ms
SS
The soft−start is activated during:
−
the startup sequence
−
the auto−recovery burst mode
Vlimit
IpFlag
/ 4.2
FB
VFB < 1.05 V ? setpoint = 250 mV
CS
LEB
250 mV
peak current
freeze
GND
Figure 2. Internal Circuit Architecture
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3
NCP1253
MAXIMUM RATINGS TABLE
Symbol
V
CC
R
qJ−A
T
J,max
Rating
Power Supply voltage, V
cc
pin, continuous voltage
Maximum voltage on low power pins CS, and FB
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model, all pins
ESD Capability, Machine Model
Value
28
−0.3
to 10
360
150
−60
to +150
2
200
Unit
V
V
°C/W
°C
°C
kV
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per Mil−Std−883, Method 3015.
Machine Model Method 200 V.
2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
=
−40°C
to +125°C, Max T
J
= 150°C, V
CC
= 12 V unless otherwise noted)
Symbol
VCC
ON
VCC
(min)
VCC
HYST
V
ZENER
ICC1
ICC2
ICC3
ICC2
ICC3
ICCstby
ICC
LATCH
ICC
LATCH
Rating
V
CC
increasing level at which driving pulses are authorized
V
CC
decreasing level at which driving pulses are stopped
Hysteresis VCC
ON
−VCC
(min)
Clamped V
CC
when latched off @ I
CC
= 500
mA
Start−up current
Internal IC consumption with I
FB
= 50
mA,
F
SW
= 65 kHz and C
L
= 0
Internal IC consumption with I
FB
= 50
mA,
F
SW
= 65 kHz and C
L
= 1 nF
Internal IC consumption with I
FB
= 50
mA,
F
SW
= 100 kHz and C
L
= 0
Internal IC consumption with I
FB
= 50
mA,
F
SW
= 100 kHz and C
L
= 1 nF
Internal IC consumption while in skip mode (V
CC
= 12 V, driving a typical
6 A/600 V MOSFET)
Current flowing into V
CC
pin that keeps the controller latched –
T
J
= 0 to 125°C
Current flowing into V
CC
pin that keeps the controller latched –
T
J
=
−40°C
to 125°C
Pin
5
5
5
5
5
5
5
5
5
5
5
5
32
40
Min
16
8.2
6
−
−
−
−
−
−
Typ
18
8.8
−
7
−
1.4
2.1
1.7
3.1
550
Max
20
9.4
−
−
15
2.2
3.0
2.5
4.0
Unit
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
DRIVE OUTPUT
T
r
T
f
R
OH
R
OL
I
source
I
sink
V
DRVlow
V
DRVhigh
Output voltage rise−time @ C
L
= 1 nF, 10−90% of output signal
Output voltage fall−time @ C
L
= 1 nF, 10−90% of output signal
Source resistance
Sink resistance
Peak source current, V
GS
= 0 V (Note 3)
Peak sink current, V
GS
= 12 V (Note 3)
DRV pin level at V
CC
close to VCC
(min)
with a 33 kW resistor to GND
DRV pin level at V
CC
= 28 V – DRV unloaded
6
6
6
6
6
6
6
6
8
10
−
−
−
−
40
30
13
6
300
500
−
12
−
14
−
−
−
−
ns
ns
W
W
mA
mA
V
V
3. Guaranteed by design
CURRENT COMPARATOR
I
IB
V
Limit1
V
Limit2
Input Bias Current @ 0.8 V input level on pin 4
Maximum internal current setpoint – T
J
= 25
°C
Maximum internal current setpoint – T
J
=
−40°
to 125
°C
4
4
4
0.744
0.72
0.02
0.8
0.8
0.856
0.88
mA
V
V
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4
NCP1253
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25°C, for min/max values T
J
=
−40°C
to +125°C, Max T
J
= 150°C, V
CC
= 12 V unless otherwise noted)
Symbol
CURRENT COMPARATOR
V
fold
V
freeze
T
DEL
T
LEB
TSS
Default internal voltage set point for frequency foldback trip point – 45% of
V
limit
Internal peak current setpoint freeze (≈31% of V
limit
)
Propagation delay from current detection to gate off−state
Leading Edge Blanking Duration
Internal soft−start duration activated upon startup, auto−recovery
4
4
4
4
−
357
250
100
300
4
150
mV
mV
ns
ns
ms
Rating
Pin
Min
Typ
Max
Unit
INTERNAL OSCILLATOR
f
OSC
f
OSC
D
max
f
jitter
f
swing
R
up
R
eq
I
ratio
V
freeze
(FB)
Oscillation frequency (65 kHz version)
Oscillation frequency (100 kHz version)
Maximum duty−ratio
Frequency jittering in percentage of f
OSC
Swing frequency
−
−
−
−
−
61
92
76
65
100
80
±5
240
71
108
84
kHz
kHz
%
%
Hz
Feedback Section
Internal pull−up resistor
Equivalent ac resistor from FB to GND
Pin 2 to current setpoint division ratio
Feedback voltage below which the peak current is frozen
2
2
−
2
20
16
4.2
1.05
V
kW
kW
FREQUENCY FOLDBACK
V
fold
F
trans
V
fold,end
V
skip
Skip
hysteresis
Frequency foldback level on the feedback pin –
≈45%
of maximum peak
current
Transition frequency below which skip−cycle occurs
End of frequency foldback feedback level, F
sw
= F
min
Skip−cycle level voltage on the feedback pin
Hysteresis on the skip comparator
−
−
−
−
22
1.5
26
350
300
30
30
V
kHz
mV
mV
mV
INTERNAL SLOPE COMPENSATION
V
ramp
R
ramp
Internal ramp level @ 25°C (Note 4)
Internal ramp resistance to CS pin
4
4
2.5
20
V
kW
4. A 1 MW resistor is connected from pin 4 to the ground for the measurement.
PROTECTIONS
V
OVP
T
OVPdel
Timer
Latched Overvoltage Protection on the V
CC
rail
Delay before OVP confirmation on the V
CC
rail
Internal auto−recovery fault timer duration
5
5
−
100
24
25.5
20
130
160
27
V
ms
ms
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