NCP1250
Current-Mode PWM
Controller for Off-line
Power Supplies
The NCP1250 is a highly integrated PWM controller capable of
delivering a rugged and high performance offline power supply in a
tiny TSOP−6 package. With a supply range up to 28 V, the controller
hosts a jittered 65 kHz or 100 kHz switching circuitry operated in peak
current mode control. When the power on the secondary side starts to
decrease, the controller automatically folds back its switching
frequency down to a minimum level of 26 kHz. As the power further
goes down, the part enters skip cycle while limiting the peak current.
Over Power Protection (OPP) is a difficult exercise especially when
no−load standby requirements drive the converter specifications. The
ON proprietary integrated OPP lets you harness the maximum
delivered power without affecting your standby performance simply
via two external resistors. An Over Voltage Protection input is also
combined on the same pin and protects the whole circuitry in case of
optocoupler failure or adverse open loop operation.
Finally, a timer−based short−circuit protection offers the best
protection scheme, letting you precisely select the protection trip point
irrespective of a loose coupling between the auxiliary and the power
windings.
Features
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1
TSOP−6
(SOT23−6)
SN SUFFIX
CASE 318G
STYLE 13
MARKING DIAGRAM
25xAYWG
G
1
25x
x
A
Y
W
G
= Specific Device Code
= A, 2, C, or D
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Fixed−Frequency 65 or 100 kHz Current−Mode Control Operation
Internal and Adjustable Over Power Protection (OPP) Circuit
Frequency Foldback Down to 26 kHz and Skip−Cycle in Light Load
Conditions
Internal Ramp Compensation
Internal Fixed 4 ms Soft−Start
100 ms Timer−Based Auto−Recovery Short−Circuit Protection
Frequency Jittering in Normal and Frequency Foldback Modes
Option for Auto−Recovery or Latched Short−Circuit Protection
OVP Input for Improved Robustness
Up to 28 V V
CC
Operation
+300 mA /
−500
mA Source/Sink Drive Capability
Less than 100 mW Standby Power at High Line
EPS 2.0 Compliant
These are Pb−Free Devices
(Note: Microdot may be in either location)
PIN CONNECTIONS
GND
FB
OPP/Latch
1
2
3
(Top View)
6
5
4
DRV
V
CC
CS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Typical Applications
ac−dc Converters for TVs, Set−top Boxes and Printers
Offline Adapters for Notebooks and Netbooks
Semiconductor Components Industries, LLC, 2011
October, 2011
−
Rev. 7
1
Publication Order Number:
NCP1250/D
NCP1250
Vbulk
.
.
OVP
Vo u t
OPP
.
NCP1250
1
2
3
6
5
4
ramp
comp.
Figure 1. Typical Application Example
Pin N5
1
2
3
Pin Name
GND
FB
OPP/OVP
Function
−
Feedback pin
Adjust the Over Power Protection
Latches off the part
Current sense + ramp
compensation
Supplies the controller
Driver output
The controller ground.
Hooking an optocoupler collector to this pin will allow regulation.
A resistive divider from the auxiliary winding to this pin sets the OPP
compensation level. When brought above 3 V, the part is fully latched
off.
This pin monitors the primary peak current but also offers a means to
introduce ramp compensation.
This pin is connected to an external auxiliary voltage and supplies the
controller.
The driver’s output to an external MOSFET gate.
Pin Description
4
5
6
CS
V
CC
DRV
OPTIONS
Controller
NCP1250ASN65T1G
NCP1250BSN65T1G
NCP1250ASN100T1G
NCP1250BSN100T1G
Frequency
65 kHz
65 kHz
100 kHz
100 kHz
OCP Latched
Yes
No
Yes
No
OCP Auto−Recovery
No
Yes
No
Yes
ORDERING INFORMATION
Device
NCP1250ASN65T1G
NCP1250BSN65T1G
NCP1250ASN100T1G
NCP1250BSN100T1G
Package Marking
25A
252
25C
25D
OCP Protection
Latch
Autorecovery
Latch
Autorecovery
Switching Frequency
65 kHz
65 kHz
100 kHz
100 kHz
TSOP−6
(Pb−Free)
3000 /
Tape & Reel
Package
Shipping
†
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NCP1250
OPP
600−ns time
constant
Vcc and logic
management
hiccup
vdd
power
on reset
UVLO
Vlatch
OVP
gone?
Up counter
RST
4
IpFlag
S
Q
Q
vdd
Rlim
Iscr
Vcc
R
Power on
reset
Frequency
modulation
1−us
blanking
65
100 kHz
clock
S
Q
Q
Clamp
R
Frequency
foldback
Vfold
Drv
Vskip
Rramp
vdd
RFB
4 ms
SS
The soft−start is activated during:
−
the startup sequence
−
the auto−recovery burst mode
IpFlag
/ 4.2
FB
VFB < 1.05 V ? setpoint = 250 mV
VOPP
CS
LEB
250 mV
peak current
freeze
+
Vlimit + VOPP
GND
Vlimit
Figure 2. Internal Circuit Architecture
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NCP1250
MAXIMUM RATINGS TABLE
Symbol
V
CC
V
DRVtran
IOPP
I
SCR
R
qJA
T
J,max
Rating
Power Supply voltage, V
CC
pin, continuous voltage
Maximum DRV pin voltage when DRV in H state, transient voltage (Note 1)
Maximum voltage on low power pins CS, FB and OPP
Maximum injected negative current into the OPP pin (pin 3)
Maximum continuous current in to the V
CC
Pin while in latched mode
Thermal Resistance Junction−to−Air
Maximum Junction Temperature
Storage Temperature Range
ESD Capability, Human Body Model (HBM), all pins
ESD Capability, Machine Model (MM)
Value
28
V
CC
+ 0.3
−0.3
to 10
−2
3
360
150
−60
to +150
2
200
Unit
V
V
V
mA
mA
C/W
C
C
kV
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The transient voltage is a voltage spike injected to DRV pin being in high state. Maximum transient duration is 100 ns.
2. This device series contains ESD protection and exceeds the following tests: Human Body Model 2000 V per Mil−Std−883, Method 3015.
Machine Model Method 200 V.
3. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.
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NCP1250
ELECTRICAL CHARACTERISTICS
(For typical values T
J
= 25C, for min/max values T
J
=
−40C
to +125C, Max T
J
= 150C, V
CC
= 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
SUPPLY SECTION
−
(For the best efficiency performance, we recommend a V
CC
below 20 V)
VCC
ON
VCC
(min)
VCC
HYST
V
ZENER
ICC1
ICC2
ICC3
ICC2
ICC3
ICC
LATCH
V
CC
increasing level at which driving pulses are authorized
V
CC
decreasing level at which driving pulses are stopped
Hysteresis VCC
ON
−
VCC
(min)
Clamped V
CC
when latched off / burst mode activation @ I
CC
= 500
mA
Start−up current
Internal IC consumption with I
FB
= 50
mA,
F
SW
= 65 kHz and C
L
= 0 nF
Internal IC consumption with I
FB
= 50
mA,
F
SW
= 65 kHz and C
L
= 1 nF
Internal IC consumption with I
FB
= 50
mA,
F
SW
= 100 kHz and C
L
= 0 nF
Internal IC consumption with I
FB
= 50
mA,
F
SW
= 100 kHz and C
L
= 1 nF
Current flowing into V
CC
pin that keeps the controller latched (Note 4)
T
J
=
−40C
to +125C
T
J
= 0C to +125C
Internal IC consumption while in skip cycle (V
CC
= 12 V, driving a typical 6 A/600 V
MOSFET)
Current−limit resistor in series with the latch SCR
5
5
5
5
5
5
5
5
5
5
40
32
550
4.0
1.4
2.1
1.7
3.1
16
8.2
6.0
7.0
15
2.2
3.0
2.5
4.0
18
8.8
20
9.4
V
V
V
V
mA
mA
mA
mA
mA
mA
ICCstby
R
lim
T
r
T
f
R
OH
R
OL
I
source
I
sink
V
DRVlow
V
DRVhigh
I
IB
V
Limit1
V
Limit2
V
fold
V
freeze
T
DEL
T
LEB
TSS
IOPPo
IOOPv
IOOPv
IOPPs
5
5
mA
kW
DRIVE OUTPUT
Output voltage rise−time @ C
L
= 1 nF, 10−90% of output signal
Output voltage fall−time @ C
L
= 1 nF, 10−90% of output signal
Source resistance
Sink resistance
Peak source current, V
GS
= 0 V – (Note 5)
Peak sink current, V
GS
= 12 V – (Note 5)
DRV pin level at V
CC
close to VCC
(min)
with a 33 kW resistor to GND
DRV pin level at V
CC
= 28 V – DRV unloaded
Input Bias Current @ 0.8 V input level on pin 4
Maximum internal current setpoint – T
J
= 25C – pin 3 grounded
Maximum internal current setpoint – T
J
=
−40C
to 125C – pin 3 grounded
Default internal voltage set point for frequency foldback trip point – 45% of V
limit
Internal peak current setpoint freeze ([31% of V
limit
)
Propagation delay from current detection to gate off−state
Leading Edge Blanking Duration
Internal soft−start duration activated upon startup, auto−recovery
Setpoint decrease for pin 3 biased to –250 mV – (Note 6)
Voltage setpoint for pin 3 biased to
−250
mV – (Note 6), T
J
= 25C
Voltage setpoint for pin 3 biased to
−250
mV – (Note 6), T
J
=
−40C
to 125C
Setpoint decrease for pin 3 grounded
6
6
6
6
6
6
6
6
8.0
10
12
14
40
30
13
6.0
300
500
ns
ns
W
W
mA
mA
V
V
CURRENT COMPARATOR
4
4
4
3
3
4
4
−
3
3
3
3
0.51
0.50
0.744
0.72
0.02
0.8
0.8
357
250
100
300
4.0
31.3
0.55
0.55
0
0.60
0.62
150
0.856
0.88
mA
V
V
mV
mV
ns
ns
ms
%
V
V
%
INTERNAL OSCILLATOR
f
OSC
f
OSC
D
max
Oscillation frequency (65 kHz version)
Oscillation frequency (100 kHz version)
Maximum duty−cycle
−
−
−
61
92
76
65
100
80
71
108
84
kHz
kHz
%
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