®
TSH321
WIDE BANDWIDTH AND MOS INPUTS
SINGLE OPERATIONAL AMPLIFIER
.
.
.
.
.
.
LOW DISTORTION
GAIN BANDWIDTH PRODUCT : 300MHz
GAIN OF 2 STABILITY
SLEW RATE : 400V/µs
VERY FAST SETTLING TIME : 60ns (0.1%)
VERY HIGH INPUT IMPEDANCE
TSH321I
-40 C, 125 C
o
o
•
•
PIN CONNECTIONS
(top view)
Offset Null 1
Inverting Input
Non-inverting Input
V
CC
1
2
3
4
8
7
6
5
Offset Null 2
V
CC
+
Output
N.C.
June 1998
1/6
321-01.EPS
321-01.TBL
DESCRIPTION:
The TSH321 is a wideband monolithic operational
amplifier, requiring a minimum close loop gain of 2
for stability.
The TSH321 features extremely high input imped-
ance (typically greater than 10
12
Ω)
allowing direct
interfacing with high impedance sources.
Low distortion, wide bandwidth and high linearity
make this amplifier suitable for RF and video appli-
cations. Short circuit protection is provided by an
internal current-limiting circuit.
The TSH321 has internal electrostatic discharge
(ESD) protection circuits and fulfills MILSTD883C-
Class2.
N
DIP8
(Plastic Package)
D
SO8
(Plastic Micropackage)
ORDER CODES
Part
Number
Temperature
Range
Package
N
D
TSH321
SCHEMATIC DIAGRAM
7 V
CC
+
non inverting
input
3
Internal
V
ref
6
output
C
c
2
inverting
input
1
Offset N1
8
Offset N2
INPUT OFFSET VOLTAGE NULL CIRCUIT
TSH321
N1
N2
100k
Ω
V
CC
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
id
V
i
I
in
T
oper
Supply Voltage
Differential Input Voltage
Input Voltage Range
Current On Offset Null Pins
Operating Free-Air Temperature Range
TSH321I
o
Parameter
321-03.EPS
Value
±
7
±
5
±
5
±
20
-40 C, 125 C
o
Unit
V
V
V
mA
o
321-02.TBL
321-03.TBL
C
OPERATING CONDITIONS
Symbol
V
CC
V
ic
Supply Voltage
Common Mode Input Voltage Range
Parameter
V
CC-
Value
±
3 to
±
6
to V
CC
-3
+
Unit
V
V
2/6
321-02.EPS
4
V
CC
-
TSH321
ELECTRICAL CHARACTERISTICS
V
CC
=
±
5V, T
amb
= 25
o
C (unless otherwise specified)
Symbol
V
io
DV
io
I
ib
I
io
I
CC
Parameter
Input Offset Voltage
T
min
≤
T
amb
≤
T
max.
Input Offset Voltage Drift
T
min
≤
T
amb
≤
T
max.
Input Bias Current
Input Offset Current
Supply Current, no load
Min.
Typ.
0.5
Max.
10
12
Unit
mV
µV/
o
C
300
200
30
28
40
32
V/V
800
300
200
-5 to +2
60
50
±
3
±
2.8
±
2.9
±
2.7
±
50
1300
850
650
-5.5 to +2.5
100
70
+3.5
-3.7
+3.3
-3.5
pA
pA
mA
10
2
2
V
CC
=
±
5V
V
CC
=
±
3V
V
CC
=
±6V
V
CC
=
±
5V
23
21
25
A
vd
T
min
≤
T
amb
≤
T
max.
Large Signal Voltage Gain
V
o
=
±2.5V
V
icm
CMR
SVR
V
o
R
L
=
∞
R
L
= 100Ω
R
L
= 50Ω
Input Common Mode Voltage Range
Common Mode Rejection Ratio
V
ic
= V
icm min.
Supply Voltage Rejection Ratio
V
CC
=
±
5V to
±
3V
Output Voltage
R
L
= 100Ω
R
L
= 50Ω
T
min
≤
T
amb
≤
T
max.
R
L
= 100Ω
R
L
= 50Ω
V
dB
dB
V
I
o
GBP
SR
e
n
K
ov
t
s
t
r
, t
f
t
d
∅m
THD
FPB
26
64
Note 1 :
Note 2 :
See test waveform figure
Full power bandwidth =
SR
Π
V
opp
3/6
321-04.TBL
Output Short Circuit Current
V
id
=
±1V,
V
o
= 0V
Gain Bandwidth Product
A
VCL
= 100, R
L
= 100Ω, C
L
= 15pF, f = 7.5MHz
Slew Rate
V
in
=
±
1V, A
VCL
= 2 R
L
= 100Ω, C
L
= 15pF
Equivalent Input Voltage Noise
R
S
= 50Ω
fo = 1kHz
fo = 10kHz
fo = 100kHz
fo = 1MHz
Overshoot
V
in
=
±
1V A
VCL
= 2, R
L
= 100Ω, C
L
= 15pF
Settling Time 0.1% - (note 1)
V
in
=
±
1V, A
VCL
= -1
Rise and Fall Time - (note 1)
V
in
=
±100mV,
A
VCL
= 2
Delay Time - (note 1)
V
in
=
±100mV,
A
VCL
= 2
Phase Margin
A
VM
= 2, R
L
= 100Ω, C
L
= 15pF
Total Harmonic Distortion
A
VCL
= 10, f = 1KHz, V
o
=
±
2.5V, no load
Full Power Bandwidth - (note 2)
V
o
= 5Vpp, R
L
= 100Ω
V
o
= 2Vpp, R
L
= 100Ω
±
100
300
mA
MHz
V/µs
200
400
nV
Hz
√
20
18.2
18.1
18.2
15
%
ns
60
ns
2
ns
2
Degrees
45
%
0.02
MHz
TSH321
TEST WAVEFORM
EVALUATION CIRCUIT
+5V
10µF
50Ω
10nF
t
s
0.1% of edge amplitude
Input
50
Ω
Output
1kΩ
10nF
90%
t
d
50%
t
r
V
in
10%
10µF
-5V
1kΩ
321-05.EPS
321-04.EPS
C
F
PRINTED CIRCUIT LAYOUT
As for any high frequency device, a few rules must
be observed when designing the PCB to get the best
performances from this high speed op amp.
From the most to the least important points :
•
Each power supply lead has to be bypassed
to ground with a 10nF ceramic capacitor very
close to the device and a 10µF tantalum ca-
pacitor.
inductance.
•
Use small resistor values to decrease time
constant with parasitic capacitance.
•
Choose component sizes as small as possible
(SMD).
•
On output, decrease capacitor load so as to
avoid circuit stability being degraded which
may cause oscillation. One can also add a
serial resistor in order to minimise its influ-
ence.
•
To provide low inductance and low resistance
common return, use a ground plane or com-
mon point return for power and signal.
•
All leads must be wide and as short as possi-
ble especially for op amp inputs. This is in
order to decrease parasitic capacitance and
•
One can add in parallel with feedback resistor
a few pF ceramic capacitor C
F
adjusted to
optimize the settling time.
4/6
TSH321
PACKAGE MECHANICAL DATA
8 PINS - PLASTIC DIP
Dimensions
A
a1
B
b
b1
D
E
e
e3
e4
F
i
L
Z
Min.
0.51
1.15
0.356
0.204
7.95
Millimeters
Typ.
3.32
Max.
Min.
0.020
0.045
0.014
0.008
0.313
Inches
Typ.
0.131
Max.
1.65
0.55
0.304
10.92
9.75
2.54
7.62
7.62
6.6
5.08
3.81
1.52
0.065
0.022
0.012
0.430
0.384
0.100
0.300
0.300
0260
0.200
0.150
0.060
5/6
DIP8.TBL
3.18
0.125
PM-DIP8.EPS
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