Radiation Hardened 3.3V Quad Differential Line
Receiver
HS-26CLV32RH, HS-26CLV32EH
The Intersil HS-26CLV32RH, HS-26CLV32EH are radiation
hardened 3.3V quad differential line receiver designed for
digital data transmission over balanced lines, in low voltage,
RS-422 protocol applications. Radiation hardened CMOS
processing assures low power consumption, high speed, and
reliable operation in the most severe radiation environments.
The HS-26CLV32RH, HS-26CLV32EH have an input sensitivity
of 200mV (Typ) over a common mode input voltage range of
-4V to
+7V.
The receivers are also equipped with input fail safe
circuitry, which causes the outputs to go to a logic “1” when
the inputs are open. The device has unique inputs that remain
high impedance when the receiver is disabled or powered-down,
maintaining signal integrity in multi-receiver applications.
Specifications for Rad Hard QML devices are controlled by the
Defense Logistics Agency Land and Maritime (DLA). The SMD
numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD
5962-95689.
A “hot-link” is provided on our
homepage for downloading.
Features
• Electrically screened to SMD #
5962-95689
• QML qualified per MIL-PRF-38535 requirements
• 1.2 micron radiation hardened CMOS
- Total dose . . . . . . . . . . . . . . . . . . . . . . . . . 300 krad(Si)(max)
- Single event upset LET . . . . . . . . . . . . . 100MeV/mg/cm
2
)
- Single event latch-up immune
• Low stand-by current . . . . . . . . . . . . . . . . . . . . . . . 13mA(max)
• Operating supply range . . . . . . . . . . . . . . . . . . . . . 3.0V to 3.6V
• Enable input levels. . . . . . . .V
IH
> (0.7)(V
DD
); V
IL
< (0.3)(V
DD
)
• CMOS output levels . . . . . . . . . . . . . .V
OH
> 2.55V; V
OL
< 0.4V
• Input fail safe circuitry
• High impedance inputs when disabled or powered-down
• Full -55°C to +125°C military temperature range
• Pb-free (RoHS compliant)
Applications
• Line receiver for MIL-STD-1553 serial data bus
Ordering Information
PART NUMBER
(Note)
5962F9568902QEC
5962F9568902QXC
5962F9568902VEC
5962F9568902VXC
5962F9666302V9A
HS0-26CLV31RH/SAMPLE
HS1-26CLV32RH/PROTO
HS9-26CLV32RH/PROTO
5962F9568904VEC
5962F9568904VXC
5962F9568904V9A
INTERNAL
MKT. NUMBER
HS1-26CLV32RH-8
HS9-26CLV32RH-8
HS1-26CLV32RH-Q
HS9-26CLV32RH-Q
HS0-26CLV31RH-Q
HS0-26CLV31RH/SAMPLE
HS1-26CLV32RH/PROTO
HS9-26CLV32RH/PROTO
HS1-26CLV32EH-Q
HS9-26CLV32EH-Q
HS0-26CLV32EH-Q
HS1- 26CLV32RH /PROTO
HS9- 26CLV32RH /PROTO
Q 5962F95 68904VEC
Q 5962F95 68904VXC
PART
MARKING
Q 5962F95 68902QEC
Q 5962F95 68902QXC
Q 5962F95 68902VEC
Q 5962F95 68902VXC
TEMP. RANGE
(°C)
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
-55 to +125
PACKAGE
(Pb-Free)
16 Ld SBDIP
16 Ld FLATPACK
16 Ld SBDIP
16 Ld FLATPACK
Die
Die
16 Ld SBDIP
16 Ld FLATPACK
16 Ld SBDIP
16 Ld FLATPACK
Die
D16.3
K16.A
D16.3
K16.A
PKG.
DWG. #
D16.3
K16.A
D16.3
K16.A
NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with
both SnPb and Pb-free soldering operations.
January 8, 2013
FN4907.4
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
|
Copyright Intersil Americas Inc. 2000, 2008, 2009, 2012, 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
HS-26CLV32RH, HS-26CLV32EH
Die Characteristics
DIE DIMENSIONS:
78 mils x 123 mils x 21 mils
(1970µm x 3120µm)
Metallization:
Bottom: Mo/TiW
Thickness: 5800
Å ±
1k
Å
Top: Al/Si/Cu
Thickness: 10k
Å ±
1k
Å
Worst Case Current Density:
<2.0 x 10
5
A/cm
2
Bond Pad Size:
110µm x 100µm
INTERFACE MATERIALS:
Glassivation:
Type: PSG (Phosphorus Silicon Glass)
Thickness: 8k
Å ±
1k
Å
Substrate:
AVLSI1RA, Silicon backside, V
DD
backside potential
Metallization Mask Layout
HS-26CLV32RH, HS-26CLV32EH
AIN
(1)
V
DD
(16)
BIN
(15)
TABLE 1. HS-26CLV32RH, HS-26CLV32EH PAD COORDINATES
PIN
NUMBER
1
2
PAD
NAME
AIN
AIN
A
OUT
ENABLE
C
OUT
CIN
CIN
GND
DIN
DIN
D
OUT
ENABLE
B
OUT
BIN
BIN
VDD
RELATIVE TO PIN 1
X COORDINATES Y COORDINATES
0
-337.1
-337.1
-337.1
-337.1
-337.1
0
418.4
776.4
1113.5
1113.5
1113.5
1113.5
1113.5
776.4
420.2
0
-362
-912.5
-1319.3
-1774.4
-2233.7
-2595.7
-2596.7
-2595.7
-2233.7
-1774.4
-1319.3
-898.4
-362
0
1
AIN (2)
(14) B
IN
3
4
5
6
A
OUT
(3)
(13) B
OUT
7
8
9
ENAB (4)
(12) ENAB
10
11
12
13
C
OUT
(5)
(11) D
OUT
14
15
16
C
IN
(6)
(10) D
IN
NOTE: Dimensions in microns
(7)
CIN
(8)
GND
(9)
DIN
For additional products, see
www.intersil.com/product_tree
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at
www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see
www.intersil.com
3
FN4907.4
January 8, 2013
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