White Electronic Designs
68040 FEATURES
Selection of Processor Speeds: 25, 33MHz
Military Temperature Range: -55°C to +125°C
Packaging
• 179 pin Ceramic PGA (P4)
• 184 lead Ceramic Quad Flatpack, CQFP (Q4)
6-Stage Pipeline, 68030-Compatible IU
68881/68882-Compatible FPU
Independent Instruction and Data MMUs
Simultaneously Accessible, 4-Kbyte Physical
Instruction Cache and 4-Kbyte Physical Data Cache
Low-Latency Bus Acceses for Reduced Cache Miss
Penalty
Multimaster/Multiprocessor Support via Bus
Snooping
Concurrent IU, FPU, MMU, and Bus Controller
Operation Maximizes Throughput
WC32P040-XXM
32-Bit, Nonmultiplexed External Address and Data
Buses with Synchronous Interface
User Object-Code Compatible with all Earlier 68000
Microprocessors
4-GigaByte Direct Addressing Range
DESCRIPTION
The WC32P040 is a 68000-compatible, high-performance,
32-bit microprocessor. The WC32P040 is a virtual
memory microprocessor employing multiple concurrent
execution units and a highly intergrated architecture that
provides very high performance in a monolithic HCMOS
device. It has a 68030-compatible integer unit (IU) and
two independent caches. The WC32P040 contains dual,
independent, demand-paged memory management units
(MMUs) for instruction and data stream accesses and
independent, 4-Kbyte instruction and data caches. The
WC32P040 has a 68881/68882-compatible floating-point
unit (FPU).
FIGURE 1 – BLOCK DIAGRAM
INSTRUCTION DATA BUS
INSTRUCTION
ATC
INSTRUCTION
FETCH
DECODE
EA
CALCULATE
EXECUTE
EA
FETCH
EXECUTE
WRITE-
BACK
FLOATING-
POINT
UNIT
WRITE-
BACK
INTEGER
UNIT
INSTRUCTION
CACHE
INSTRUCTION
ADDRESS
B
U
S
C
O
N
T
R
O
L
L
E
R
CONVERT
INSTRUCTION
MMU/CACHE/SNOOP
CONTROLLER
INSTRUCTION MEMORY UNIT
ADDRESS
BUS
DATA MEMORY UNIT
DATA
MMU/CACHE/SNOOP
CONTROLLER
DATA
BUS
DATA
ADDRESS
BUS
CONTROL
SIGNALS
DATA
ATC
DATA
CACHE
OPERAND DATA BUS
July 1998
July 1998
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WC32P040-XXM
FIGURE 2 –
PIN CONFIGURATION FOR WC32P040-XXM, CQFP (Q4)
GND
GND
A
31
A
30
V
CC
A
29
A
28
GND
A
27
A
26
V
CC
A
25
A
24
GND
A
23
A
22
V
CC
A
21
A
20
GND
A
19
A
18
V
CC
GND
A
17
A
16
GND
A
15
A
14
V
CC
A
13
A
12
GND
A
11
A
10
GND
V
CC
TT
1
TT
0
GND
UPA
1
UPA
0
V
CC
CIOUT#
IPEND#
GND
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
D
0
D
1
V
CC
GND
D
2
D
3
GND
D
4
GND
D
5
V
CC
D
6
D
7
GND
D
8
D
9
V
CC
GND
D
10
D
11
GND
D
12
D
13
V
CC
D
14
D
15
GND
D
16
D
17
V
CC
GND
D
18
D
19
GND
D
20
D
21
V
CC
D
22
V
CC
D
23
GND
D
24
D
25
GND
V
CC
D
26
TOP VIEW
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
D
27
GND
D
28
D
29
V
CC
D
30
D
31
GND
GND
A
9
A
8
V
CC
A
7
A
6
GND
A
5
A
4
V
CC
A
3
A
2
GND
A
1
A
0
V
CC
GND
TM
2
TM
1
GND
TM
0
TLN
1
V
CC
TLN
0
SIZ
0
GND
R/W#
LOCKE#
V
CC
GND
SIZ
1
LOCK#
GND
MI#
BR#
V
CC
TS#
BB#
Pin Group
PLL
Internal Logic
Output Drivers
17, 22, 24
July 1998
RSTO#
TD
0
TD
1
TCK
GND
TRST#
TMS
GND
V
CC
MDIS#
CDIS#
RSTI#
IPL
2#
IPL
1#
IPL
0#
GND
GND
BCLK
V
CC
GND
V
CC
GND
PCLK
GND
GND
DLE
GND
GND
TCI#
AVEC#
TBI#
V
CC
GND
SC
0
SC
1
BG#
TEA#
TA#
PST
0
GND
PST
1
PST
2
V
CC
PST
3
TIP
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
GND
19, 21
5, 8, 10, 27, 28, 33, 55, 68, 95, 108, 121, 130,
135, 162, 174
16, 20, 25, 40, 46, 52, 59, 65, 72, 78, 84, 85,
91, 98, 105, 112, 118, 125, 132, 139, 140, 146,
152, 158, 165, 171, 178, 184
Vcc
9, 32, 56, 69, 81, 94, 100, 109, 122, 136, 149,
161, 175
43, 49, 62, 75, 88, 102, 115, 128, 143, 155,
168, 181
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WC32P040-XXM
FIGURE 3 –
PIN CONFIGURATION FOR WC32P040-XXM, PGA (P4)
T
S
R
Q
UPA
1
P
A
10
N
A
12
M
A
13
L
K
J
H
G
F
E
D
C
B
A
A
14
A
15
A
17
A
18
A
20
A
21
A
22
A
24
A
27
A
29
A
31
1
TDO TRST# GND CDIS# IPL
2
# IPL
1
# IPL
0
#
IPEND# GND
TDI
TCK
TMS MDIS# RSTI#
V
CC
GND
BCLK
V
CC
V
CC
DLE
GND
PCLK
TCI# AVEC# SC
0
GND
GND
TBI#
GND
SC
1
V
CC
BG#
TEA#
GND
TA#
PST
1
PST
2
PST
0
GND
TIP#
PST
3
V
CC
TS#
MI#
SIZ
1
R/W#
GND
V
CC
GND
V
CC
V
CC
A
6
A
9
D
29
D
27
BB#
BR#
GND LOCK#
V
CC
LOCKE#
GND
SIZ
0
GND
V
CC
GND
TM
2
A
2
GND
V
CC
GND
D
30
GND
V
CC
GND
D
21
17
TLN
0
TLN
1
TM
0
TM
1
A
0
A
1
A
3
A
4
A
5
A
7
A
8
D
31
D
28
D
26
D
24
18
CIOUT# V
CC
RTSO# GND
GND
TT1
GND
V
CC
GND
A
16
A
19
GND
V
CC
GND
A
26
GND
V
CC
GND
D
3
2
UPA
0
TT
0
A
11
V
CC
GND
GND
V
CC
V
CC
A
23
A
25
A
28
A
30
D
0
D
1
D
4
3
D
2
GND
D
5
4
BOTTOM VIEW
V
CC
V
CC
D
6
5
GND
GND
D
7
6
GND
D
8
D
9
7
V
CC
GND
D
10
8
GND
V
CC
D
11
9
V
CC
GND
D
12
10
GND
D
16
D
13
11
V
CC
D
18
D
14
12
GND
GND
D
15
13
V
CC
V
CC
D
17
14
D
23
GND
D
19
15
D
25
D
22
D
20
16
Pin Group
PLL
Internal Logic
Output Drivers
S9, R6, R10
GND
R8, S8
C6, C7, C9, C11, C13, K3, L3, M16, R4, R11,
R13, S6, S10, T4
B2, B4, B6, B8, B10, B13, B15, B17, D2, D17,
F2, F17, H2, H17, L2, L17, N2, N17, Q2, Q17,
S2, S15, S17
Vcc
C5, C8, C10, C12, C14, H3, H16, J3, J16,
L16, M3, R5, R12
B5, B9, B14, C2, C17, G2, G17, M2, M17, R2,
R17, S16
July 1998
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
DATA FORMATS
The WC32P040 supports the basic data formats of the
68000 family. Some data formats apply only to the IU,
some only to the FPU, and some to both. In addition, the
instruction set supports operations on other data formats
such as memory addresses.
WC32P040-XXM
ADDRESSSING
The WC32P040 supports the basic addressing modes of
the 68000 family. The register indirect addressing modes
support postincrement, predecrement, offset, and indexing.
The program counter indirect mode also has indexing and
offset capabilities.
DATA FORMATS
Operand Data
Format
Bit
Bit Field
Binary-Coded
Decimal (BCD)
Byte Integer
Word Integer
Long-Word Integer
Quad-Word Integer
16-Byte
Single-Precision Real
Double-Precision
Real
Extended-Precision
Real
Size
1 Bit
1-32 Bits
8 Bits
8 Bits
16 Bits
32 Bits
64 Bits
128 Bits
32 Bits
64 Bits
80 Bits
Supported In
IU
IU
IU
IU, FPU
IU, FPU
IU, FPU
IU
IU
FPU
FPU
FPU
Notes
—
Field of Consecutive Bits
Packed: 2 Digits/Byte;
Unpacked: 1 Digit/Byte
—
—
—
Any Two Data Registers
Memory Only, Aligned to
16-Byte Boundary
1-Bit Sign, 8-Bit Exponent,
23-Bit Fraction
1-Bit Sign,11-Bit
Exponent, 52-Bit Fraction
1-Bit Sign,15-Bit
Exponent, 64-Bit Mantissa
ADDRESSING MODES
Addressing
Register Direct
Data Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
Syntax
Dn
An
(An)
(An) +
- (An)
(d16,An)
(d8,An,Xn)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d16,PC)
(d8,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
(xxx).W
(xxx).L
#<xxx>
INSTRUCTION SET SUMMARY
Opcode
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
Operation
BCD Source + BCD Destination + X
Source + Destination
Source + Destination
Destination
Destination
Destination
Destination
Destination
Syntax
ABCD Dy,Dx
ABCD -(Ay),-(Ax)
ADD <ea>,Dn
ADD Dn,<ea>
ADDA <ea>,An
ADDI #<data>,<ea>
ADDQ #<data>,<ea>
ADDX Dy,Dx
ADDX -(Ay),-(Ax)
AND <ea>,Dn
AND Dn,<ea>
ANDI #<data>,<ea>
ANDI #<data>,CCR
SR
ANDI #<data>,SR
Immediate Data + Destination
Immediate Data + Destination
Source + Destination + X
Source
Λ
Destination
Destination
Destination
Destination
Immediate Data
Λ
Destination
Source
Λ
CCR
CCR
If supervisor state
then Source
Λ
SR
else TRAP
July 1998
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
INSTRUCTION SET SUMMARY (contd)
Opcode
ASL,ASR
Operation
Destination Shifted by count
Destination
Syntax
ASd Dx,Dy
(1)
ASd #<data>,Dy
(1)
ASd <ea>
(1)
Bcc <label>
Z;
(bit number) of Destination
BCHG Dn,<ea>
BCHG #<data>,<ea>
BCLR Dn,<ea>
BCLR #<data>,<ea>
BFCHG <ea> {offset:width}
BFCLR <ea> {offset:width}
BFEXTS <ea> {offset:width}, Dn
BFEXTU <ea> {offset:width}, Dn
Dn
BFFFO <ea> {offset:width}, Dn
BFINS Dn,<ea> {offset:width}
BFSET <ea> {offset:width}
BFTST <ea> {offset:width}
BKPT #<data>
BRA <label>
BSET Dn,<ea>
BSET #<data>,<ea>
PC
BSR <label>
BTST Dn,<ea>
BTST #<data>,<ea>
cc;
CAS Dc,Du,<ea>
WC32P040-XXM
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CAS
It condition true
then PC + dn
PC
~(bit number of Destination)
~(bit number ot Destination)
~(bit number ot Destination) Z;
0 bit number ot Destination
~(bit
fi
eld ot Destination)
0
bit
fi
eld of Destination
Dn
Dn
bit
fi
eld of Source
bit offset of Source
Dn
1s
bit
fi
eld of Destination
bit offset of Source Bit Scan
bit
fi
eld of Destination
bit
fi
eld of Destination
bit
fi
eld of Destination
Run breakpoint acknowledge cycle; TRAP as illegal instruction
PC+dn
PC
~(bit number ot Destination) Z;
1 bit number of Destination
SP - 4
SP; PC
(SP); PC + dn
Z
–(bit number of Destination)
CAS Destination – Compare Operand
if Z, Update Operand Destination
else Destination Compare Operand
CAS2 Destination 1 – Compare 1 cc;
if Z, Destination 2 – Compare cc;
if Z, Update 1 Destination 1;
Update 2 Destination 2
else Destination 1 Compare 1;
Destination 2 Compare 2
If Dn < 0 or Dn > Source then TRAP
If Rn < LB or If Rn > UB then TRAP
If supervisor state
then invalidate selected cache lines
else TRAP
0
Destination
cc
Destination – Source
Destination – Source
Destination – Immediate Data
Destination – Source
cc
CAS2
CAS2 Dc1-Dc2,Du1-Du2,(Rn1)-(Rn2)
CHK
CHK2
CINV
CHK <ea>,Dn
CHK2 <ea>,Rn
CINVL <caches>,
(An) CINVP <caches>,
(An) CINVA <caches>
CLR <ea>
CMP <ea>,Dn
CMPA <ea>,An
CMPI #<data>,<ea>
CMPM (Ay)+,(Ax)+
CMP2 <ea>,Rn
CPUSHL <caches>, (An)
CPUSHP <caches>, (An)
CPUSHA <caches>
CLR
CMP
CMPA
CMPI
CMPM
CMP2
CPUSH
Compare Rn < LB or Rn > UB and Set Condition Codes
If supervisor state
then it data cache push selected dirty data cache lines;
invalidate selected cache lines
else TRAP
5
July 1998
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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