Asynchronous operation for compatibility with industry-
standard 512K x 8 SRAMs
q
TTL compatible inputs, output levels specified for both TTL
and CMOS loads, three-state bidirectional data bus
q
3.3 + 0.3V power supply
q
Typical radiation performance
- Intrinsic total-dose: 30 krad(Si)
- Space environment shields to >100 krad(Si)
- SEL Immune >100 MeV-cm
2
/mg
- Onset LET < 10 MeV-cm
2
/mg
- Memory Cell Saturated Cross Section, 6.1E-10cm
2
- 1.0E-11errors/bit-day, Adams to 90% geosynchronous
heavy ion
- Inherent Neutron Hardness: 3.0E14n/cm
2
- Dose Rate
- Upset 1.0E9 rad(Si)/sec
- Latchup >1.0E11 rad(Si)/sec
q
Packaging options:
- 36-lead ceramic flatpack
q
Standard Microcircuit Drawing 5962-99607
- QML compliant part
Clk. Gen.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
INTRODUCTION
The UT8Q512 is a high-performance CMOS static RAM
organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (E1),
an active LOW Output Enable (G), and three-state drivers.
This device has a power-down feature that reduces power
consumption by more than 90% when deselected
.
Writing to the device is accomplished by taking Chip Enable
one (E1) input LOW and Write Enable (W) inputs LOW.
Data on the eight I/O pins (DQ
0
through DQ
7
) is then written
into the location specified on the address pins (A
0
through
A
18
). Reading from the device is accomplished by taking
Chip Enable one (E1) and Output Enable (G) LOW while
forcing Write Enable (W) HIGH. Under these conditions,
the contents of the memory location specified by the address
pins will appear on the I/O pins.
The eight input/output pins (DQ
0
through DQ
7
) are placed
in a high impedance state when the device is deselected ( E1,
HIGH), the outputs are disabled (G HIGH), or during a write
operation (E1 LOWand W LOW).
Pre-Charge Circuit
Row Select
Memory Array
1024 Rows
512x8 Columns
I/O Circuit
Column Select
Data
Control
CLK
Gen.
A10
A11
A12
A13
A14
A15
A16
A17
A18
DQ
0
- DQ
7
E
W
G
Figure 1. UT8Q512 SRAM Block Diagram
DEVICE OPERATION
A0
A1
A2
A3
A4
E1
DQ0
DQ1
V
DD
V
SS
DQ2
DQ3
W
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
G
DQ7
DQ6
V
SS
V
DD
DQ5
DQ4
A14
A13
A12
A11
A10
NC
The UT8Q512 has three control inputs called Enable 1 (E1),
Write Enable (W), and Output Enable (G); 19 address inputs,
A(18:0); and eight bidirectional data lines, DQ(7:0). E1 Device
Enable controls device selection, active, and standby modes.
Asserting E1 enables the device, causes I
DD
to rise to its active
value, and decodes the 19 address inputs to select one of 524,288
words in the memory. W controls read and write operations.
During a read cycle, G must be asserted to enable the outputs.
Table 1. Device Operation Truth Table
G
X
X
W
X
0
1
1
E1
1
0
0
0
I/O Mode
3-state
Data in
3-state
Data out
Mode
Standby
Write
Read
2
Read
Figure 2. UT8Q512 25ns SRAM Pinout
1
0
PIN NAMES
A(18:0)
DQ(7:0)
E1
Address
Data Input/Output
Enable
W
G
V
DD
V
SS
Write Enable
Output Enable
Power
Ground
Notes:
1. “X” is defined as a “don’t care” condition.
2. Device active; outputs disabled.
READ CYCLE
A combination of W greater than V
IH
(min) and E1 less than
V
IL
(max) defines a read cycle. Read access time is measured
from the latter of Device Enable, Output Enable, or valid address
to valid data output.
SRAM Read Cycle 1, the Address Access in figure 3a, is
initiated by a change in address inputs while the chip is enabled
with G asserted and W deasserted. Valid data appears on data
outputs DQ(7:0) after the specified t
AVQV
is satisfied. Outputs
remain active throughout the entire cycle. As long as Device
Enable and Output Enable are active, the address inputs may
change at a rate equal to the minimum read cycle time (t
AVAV
).
SRAM read Cycle 2, the Chip Enable - Controlled Access in
figure 3b, is initiated by E1 going active while G remains
asserted, W remains deasserted, and the addresses remain stable
for the entire cycle. After the specified t
ETQV
is satisfied, the
eight-bit word addressed by A(18:0) is accessed and appears at
the data outputs DQ(7:0).
SRAM read Cycle 3, the Output Enable - Controlled Access in
figure 3c, is initiated by G going active while E1 is asserted, W
is deasserted, and the addresses are stable. Read access time is
t
GLQV
unless t
AVQV
or t
ETQV
have not been satisfied.
2
WRITE CYCLE
A combination of W less than V
IL
(max) and E1 less than
V
IL
(max) defines a write cycle. The state of G is a “don’t care”
for a write cycle. The outputs are placed in the high-impedance
state when either G is greater than V
IH
(min), or when W is less
than V
IL
(max).
Write Cycle 1, the Write Enable - Controlled Access in figure
4a, is defined by a write terminated by W going high, with E1
still active. The write pulse width is defined by t
WLWH
when the
write is initiated by W, and by t
ETWH
when the write is initiated
by E1. Unless the outputs have been previously placed in the
high-impedance state by G, the user must wait t
WLQZ
before
applying data to the nine bidirectional pins DQ(7:0) to avoid bus
contention.
Write Cycle 2, the Chip Enable - Controlled Access in figure
4b, is defined by a write terminated by the latter of E1 going
inactive. The write pulse width is defined by t
WLEF
when the
write is initiated by W, and by t
ETEF
when the write is initiated
by the E1going active. For the W initiated write, unless the
outputs have been previously placed in the high-impedance state
by G, the user must wait t
WLQZ
before applying data to the eight
bidirectional pins DQ(7:0) to avoid bus contention.
TYPICAL RADIATION HARDNESS
Table 2. Radiation Hardness
Design Specifications
1
Total Dose
Heavy Ion
Error Rate
2
30
1E-11
krad(Si)
Errors/Bit-Day
Notes:
1. The SRAM will not latchup during radiation exposure under recommended
operating conditions.
2. 10% worst case particle environment, Geosynchronous orbit, 0.025 mils of
Aluminum.
3
ABSOLUTE MAXIMUM RATINGS
1
(Referenced to V
SS
)
SYMBOL
V
DD
V
I/O
T
STG
P
D
T
J
Θ
JC
I
I
PARAMETER
DC supply voltage
Voltage on any pin
Storage temperature
Maximum power dissipation
Maximum junction temperature
2
Thermal resistance, junction-to-case
3
DC input current
LIMITS
-0.5 to 4.6V
-0.5 to 4.6V
-65 to +150°C
1.0W
+150°C
10°C/W
±
10 mA
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life.
3. Test per MIL-STD-883, Method 1012.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
DD
T
C
V
IN
PARAMETER
Positive supply voltage
Case temperature range
DC input voltage
LIMITS
3.0 to 3.6V
-55 to +125°C
0V to V
DD
4
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)*
(-55°C to +125°C) (V
DD
= 3.3V + 0.3)
SYMBOL
V
IH
V
IL
V
OL1
V
OL2
V
OH1
V
OH2
C
IN1
C
IO1
I
IN
I
OZ
PARAMETER
High-level input voltage
Low-level input voltage
Low-level output voltage
Low-level output voltage
High-level output voltage
High-level output voltage
Input capacitance
Bidirectional I/O capacitance
Input leakage current
Three-state output leakage current
(CMOS)
(CMOS)
I
OL
= 200µA,V
DD
=3.0V(CMOS)
I
OL
= 8mA, V
DD
=3.0V(TTL)
I
OH
= -200µA,V
DD
=3.0V(CMOS)
I
OH
= -4mA,V
DD
=3.0V(TTL)
ƒ
= 1MHz @ 0V
ƒ
= 1MHz @ 0V
V
IN
= V
DD
and V
SS
V
O
= V
DD
and V
SS
V
DD
= V
DD
(max)
G = V
DD
(max)
I
OS2, 3
I
DD
(OP)
Short-circuit output current
V
DD
= V
DD
(max), V
O
= V
DD
V
DD
= V
DD
(max), V
O
= 0V
Supply current operating
@ 1MHz
Inputs: V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD
- 0.2V
I
OUT
= 0mA
V
DD
= V
DD
(max)
I
DD1
(OP)
Supply current operating
@40MHz,
Inputs: V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD
- 0.2V
I
OUT
= 0mA
V
DD
= V
DD
(max)
I
DD2
(SB)
4
Supply current standby
@0MHz,
Inputs: V
IL
= V
SS
+ 0.2V,
V
IH
= V
DD
- 0.2V
I
OUT
= 0mA
E1 = V
DD
- 0.5, V
DD
= V
DD
(max)
Notes:
* Post-radiation performance guaranteed at 25°C per MIL-STD-883 Method 1019 at 3.0E4 rad(Si).
1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance.
2. Supplied as a design limit but not guaranteed or tested.
3. Not more than one output may be shorted at a time for maximum duration of one second.
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