ESD Protection (all pins, Human Body Model) ...................±2kV
Operating Temperature Range ........................ -40NC to +125NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Soldering Temperature (reflow) ......................................+260NC
Lead Temperature (soldering,10s) .................................+300NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (q
JA
) ..........29°C/W
Junction-to-Case Thermal Resistance (q
JC
) .................2°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= -40NC to +125NC, unless otherwise noted.) (Notes 2 and 3)
PARAMETER
V
DD
DVDD
Input Logic 0
Input Logic 1
Analog Voltages
(FORCE+,FORCE2, FORCE-,
RTDIN+, RTDIN-)
Reference Resistor
Cable Resistance
R
REF
R
CABLE
Per lead
SYMBOL
V
DD
V
DVDD
V
IL
V
IH
CS,
SDI, SCLK
CS,
SDI, SCLK
CONDITIONS
MIN
3.0
3.0
-0.3
0.7 x
V
DVDD
0
350
0
TYP
3.3
3.3
MAX
3.6
3.6
0.3 x
V
DVDD
V
DVDD
+ 0.3
V
BIAS
10k
50
UNITS
V
V
V
V
Normal conversion results
V
I
I
ELECTRICAL CHARACTERISTICS
(3.0V
P
V
DD
P
3.6V, T
A
= -40NC to +125NC, unless otherwise noted. Typical values are T
A
= +25NC, V
DD
= V
DVDD
= 3.3V.) (Notes 2
and 3)
PARAMETER
ADC Resolution
ADC Full-Scale Input Voltage
(RTDIN+ - RTDIN-)
SYMBOL
CONDITIONS
No missing codes
MIN
TYP
15
REFIN+ -
REFIN-
MAX
UNITS
Bits
V
Maxim Integrated
2
MAX31865
RTD-to-Digital Converter
ELECTRICAL CHARACTERISTICS (continued)
(3.0V
P
V
DD
P
3.6V, T
A
= -40NC to +125NC, unless otherwise noted. Typical values are T
A
= +25NC, V
DD
= V
DVDD
= 3.3V.) (Notes 2
and 3)
PARAMETER
ADC Common-Mode Input
Range
RTDIN+, RTDIN-, 0NC to +70NC, on-state
Input Leakage Current
Bias Voltage
Bias Voltage Output Current
Bias Voltage Load Regulation
Bias Voltage Startup Time
ADC Full-Scale Error
ADC Integral Nonlinearity
ADC Offset Error
Noise (over Nyquist Bandwidth)
Common-Mode Rejection
50/60Hz Noise Rejection
Temperature Conversion Time
(Note 5)
Automatic Fault Detection Cycle
Time
Power-Supply Rejection
Power-Supply Current (Note 6)
Power-On Reset Voltage
Threshold
Power-On Reset Voltage
Hysteresis
Input Capacitance
Input Leakage Current
Output High Voltage
Output Low Voltage
C
IN
I
L
V
OH
V
OL
Logic inputs
Logic inputs
I
OUT
= -1.6mA
I
OUT
= 1.6mA
-1
V
DVDD
- 0.4
0.4
I
DD
Shutdown
I
DD
Bias off, ADC off
Bias on, active conversion
2
Fundamental and harmonics
Continuous conversion (60Hz notch)
t
CONV
Single conversion (60Hz notch)
Single conversion (50Hz notch)
Continuous conversion (50Hz notch)
From
CS
high to cycle complete
Input referred
Differential Input, endpoint fit, 0.3 x V
BIAS
P
V
REF
P
V
BIAS
-3
150
90
82
16.7
52
62.5
20
550
1
1.5
2
2.27
120
6
+1
3
3.5
17.6
55
66
21
600
Fs
LSB/V
mA
mA
V
mV
pF
FA
V
V
ms
V
BIAS
I
OUT
I
OUT
P
5.75mA
(Note 4)
±1
±1
+3
RTDIN+, RTDIN-, -40NC to +85NC, on-state
RTDIN+, RTDIN-, -40NC to 100NC, on-state
1.95
0.2
30
10
SYMBOL
CONDITIONS
MIN
0
2
5
14
2.00
2.06
5.75
V
mA
mV/mA
ms
LSB
LSB
LSB
FV
RMS
dB
dB
nA
TYP
MAX
V
BIAS
UNITS
V
Maxim Integrated
3
MAX31865
RTD-to-Digital Converter
AC ELECTRICAL CHARACTERISTICS: SPI INTERFACE
(3.0V
P
V
DD
P
3.6V, T
A
= -40NC to +125NC, unless otherwise noted. Typical values are T
A
= +25NC, V
DD
= V
DVDD
= 3.3V.) (Notes 3
and 7) (Figure
1
and
Figure 2)
PARAMETER
Data to SCLK Setup
SCLK to Data Hold
SCLK to Data Valid
SCLK Low Time
SCLK High Time
SCLK Frequency
SCLK Rise and Fall
CS
to SCLK Setup
SCLK to
CS
Hold
CS
Inactive Time
CS
to Output High-Z
Address 01h or 02h Decoded to
DRDY
High
SYMBOL
t
DC
t
CDH
t
CDD
t
CL
t
CH
t
CLK
t
R
, t
F
t
CC
t
CCH
t
CWH
t
CDZ
t
DRDYH
(Notes 8, 9)
(Notes 8, 9)
(Notes 8, 9, 10)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Note 9)
(Notes 8, 9)
After RTD register read access (Note 9)
50
400
100
400
40
100
100
DC
5.0
200
CONDITIONS
MIN
35
35
80
TYP
MAX
UNITS
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
Note 2:
All voltages are referenced to ground when common. Currents entering the IC are specified positive.
Note 3:
Limits are 100% production tested at T
A
= +25°C and/or T
A
= +85°C. Limits over the operating temperature range and rel-
evant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 4:
For 15-bit settling, a wait of at least 10.5 time constants of the input RC network is required. Max startup time is calculated
with a 10kω reference resistor and a 0.1µF capacitor across the RTD inputs.
Note 5:
The first conversion after enabling continuous conversion mode takes a time equal to the single conversion time for the
respective notch frequency.
Note 6:
Specified with no load on the bias pin as the sum of analog and digital currents. No active communication. If the RTD
input voltage is greater than the input reference voltage, then an additional 400µA I
DD
can be expected.
Note 7:
All timing specifications are guaranteed by design.
Note 8:
Measured at V
IH
= 0.7V x V
DVDD
or V
IL
= 0.3 x V
DVDD
and 10ms maximum rise and fall times.
Note 9:
Measured with 50pF load.
Note 10:
Measured at V
OH
= 0.7 x V
DVDD
or V
OL
= 0.3 x V
DVDD
. Measured from the 50% point of SCLK to the V
OH
minimum of
SDO.
Maxim Integrated
4
MAX31865
RTD-to-Digital Converter
CS
t
CC
SCLK
t
CDH
t
DC
SDI
A7
A6
A0
t
CDZ
SDO
D7
D6
D1
D0
t
CDD
t
CDD
WRITE ADDRESS BYTE
NOTE:
SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1.
READ DATA BYTE
Figure 1. Timing Diagram: SPI Read Data Transfer
CS
t
CC
t
CL
SCLK
t
CDH
t
DC
SDI
A7
A6
A0
D7
t
CH
t
CDH
t
CWH
t
R
t
F
t
CCH
D0
WRITE ADDRESS BYTE
NOTE:
SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1.
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