D2
PA
K
PSMN2R8-80BS
N-channel 80 V, 3 mΩ standard level FET in D2PAK
Rev. 2 — 29 February 2012
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel MOSFET in D2PAK package qualified to 175C. This product is
designed and qualified for use in a wide range of industrial, communications and domestic
equipment.
1.2 Features and benefits
High efficiency due to low switching
and conduction losses
Suitable for standard level gate drive
1.3 Applications
DC-to-DC converters
Load switch
Motor control
Server power supplies
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
T
j
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
junction temperature
drain-source on-state
resistance
V
GS
= 10 V; I
D
= 25 A; T
j
= 100 °C;
see
Figure 12;
see
Figure 13
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 13
Dynamic characteristics
Q
GD
Q
G(tot)
E
DS(AL)S
gate-drain charge
total gate charge
non-repetitive
drain-source
avalanche energy
V
GS
= 10 V; I
D
= 75 A; V
DS
= 40 V;
see
Figure 14;
see
Figure 15
-
-
-
27
139
-
-
-
676
nC
nC
mJ
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
mb
= 25 °C; V
GS
= 10 V; see
Figure 1
T
mb
= 25 °C; see
Figure 2
[1]
Min
-
-
-
-55
-
-
Typ
-
-
-
-
4.21
2.55
Max
80
120
306
175
5
3
Unit
V
A
W
°C
mΩ
mΩ
Static characteristics
Avalanche ruggedness
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 120 A;
V
sup
≤
80 V; R
GS
= 50
Ω;
unclamped
[1]
Continuous current is limited by package.
NXP Semiconductors
PSMN2R8-80BS
N-channel 80 V, 3 mΩ standard level FET in D2PAK
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
[1]
source
drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
2
1
3
SOT404 (D2PAK)
[1]
It is not possible to make connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
PSMN2R8-80BS
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
T
sld(M)
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
peak soldering temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 120 A;
V
sup
≤
80 V; R
GS
= 50
Ω;
unclamped
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1
pulsed; t
p
≤
10 µs; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
[1]
[1]
Min
-
-
-20
-
-
-
-
-55
-55
-
-
-
-
Max
80
80
20
120
120
824
306
175
175
260
120
824
676
Unit
V
V
V
A
A
A
W
°C
°C
°C
A
A
mJ
Source-drain diode
Avalanche ruggedness
[1]
Continuous current is limited by package.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
PSMN2R8-80BS
Product data sheet
Rev. 2 — 29 February 2012
2 of 14
NXP Semiconductors
PSMN2R8-80BS
N-channel 80 V, 3 mΩ standard level FET in D2PAK
240
I
D
(A)
180
003aaf615
120
P
der
(%)
80
03aa16
120
(1)
40
60
0
0
50
100
150
200
T
mb
(
°
C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Continuous drain current as a function of
mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
003aag771
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/ I
D
t
p
=10
μ
s
100
μ
s
10
DC
1 ms
1
10 ms
100 ms
10
-1
10
-1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PSMN2R8-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 29 February 2012
3 of 14
NXP Semiconductors
PSMN2R8-80BS
N-channel 80 V, 3 mΩ standard level FET in D2PAK
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to mounting base
thermal resistance from junction
to ambient
Conditions
see
Figure 4
minimum footprint; mounted on a
printed-circuit board
Min
-
-
Typ
0.22
50
Max
0.49
-
Unit
K/W
K/W
1
Z
th(j-mb)
(K/W)
003aag773
10
-1
δ
= 0.5
0.2
0.1
0.05
10
-2
0.02
P
δ
=
tp
T
single shot
tp
t
10
-3
10
-6
T
10
-5
10
-4
10
-3
10
-2
10
-1
t
p (s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PSMN2R8-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 29 February 2012
4 of 14
NXP Semiconductors
PSMN2R8-80BS
N-channel 80 V, 3 mΩ standard level FET in D2PAK
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source
breakdown voltage
gate-source threshold
voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
see
Figure 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 10
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 10;
see
Figure 11
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 80 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 80 V; V
GS
= 0 V; T
j
= 175 °C
V
GS
= -20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 25 A; T
j
= 175 °C;
see
Figure 12;
see
Figure 13
V
GS
= 10 V; I
D
= 25 A; T
j
= 100 °C;
see
Figure 12;
see
Figure 13
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 13
R
G
internal gate resistance f = 1 MHz
(AC)
total gate charge
gate-source charge
pre-threshold
gate-source charge
post-threshold
gate-source charge
gate-drain charge
gate-source plateau
voltage
input capacitance
output capacitance
reverse transfer
capacitance
turn-on delay time
rise time
turn-off delay time
fall time
V
DS
= 40 V; R
L
= 0.53
Ω;
V
GS
= 5 V;
R
G(ext)
= 10
Ω;
I
D
= 75 A
I
D
= 75 A; V
DS
= 40 V;see
Figure 14;
see
Figure 15
V
DS
= 40 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 16
I
D
= 0 A; V
DS
= 0 V; V
GS
= 10 V
I
D
= 75 A; V
DS
= 40 V; V
GS
= 10 V;
see
Figure 14;
see
Figure 15
Min
73
80
1
-
2
-
-
-
-
-
-
-
-
Typ
-
-
-
-
3
0.02
-
10
10
6.12
4.21
2.55
0.9
Max
-
-
-
4.6
4
10
500
100
100
7.2
5
3
-
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Ω
Static characteristics
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GS(th)
Q
GS(th-pl)
Q
GD
V
GS(pl)
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
-
-
-
-
-
-
-
-
-
-
-
-
-
-
135
139
51
30
21
27
5.8
9961
847
401
41
43
109
44
-
-
-
-
-
-
-
-
-
-
-
-
-
-
nC
nC
nC
nC
nC
nC
V
pF
pF
pF
ns
ns
ns
ns
PSMN2R8-80BS
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2 — 29 February 2012
5 of 14
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