EXPOSED PAD (PIN 17) PCB CONNECTION TO GND IS OPTIONAL
orDer inForMaTion
LEAD FREE FINISH
LTC6820IUD#PBF
LTC6820HUD#PBF
LTC6820IMS#PBF
LTC6820HMS#PBF
TAPE AND REEL
LTC6820IUD#TRPBF
LTC6820HUD#TRPBF
LTC6820IMS#TRPBF
LTC6820HMS#TRPBF
PART MARKING*
LGFM
LGFM
6820
6820
PACKAGE DESCRIPTION
16-Lead (3mm
×
3mm) Plastic QFN
16-Lead (3mm
×
3mm) Plastic QFN
16-Lead Plastic MSOP
16-Lead Plastic MSOP
SPECIFIED TEMPERATURE RANGE
–40°C to 85°C
–40°C to 125°C
–40°C to 85°C
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on nonstandard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
6820f
2
LTC6820
The
l
denotes the specifications which apply over the full specified
temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 2.7V to 5.5V, V
DDS
= 1.7V to 5.5V, R
BIAS
= 2k to 20k unless
otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
Power Supply
Operating Supply Voltage Range
V
DD
IO Supply Voltage Range (Level Shifting)
V
DDS
Supply Current, READY/ACTIVE States
I
DD
(Note 4)
CONDITIONS
l
elecTrical characTerisTics
MIN
2.7
1.7
4
1.3
TYP
MAX
5.5
5.5
5.8
2.9
6
3
1
UNITS
V
V
mA
mA
mA
mA
µA
µA
µA
Supply Current, IDLE State
I
DDS
Biasing
V
BIAS
I
B
A
IB
V
A
V
ICMP
I
LEAK(ICMP)
I
LEAK(IP/IM)
A
TCMP
IO Supply Current (Note 5)
Affects
CS,
SCK, MOSI, MISO and EN Pins
R
BIAS
= 2kΩ (I
B
= 1mA)
1/t
CLK
= 0MHz
1/t
CLK
= 1MHz
1/t
CLK
= 0MHz
R
BIAS
= 20kΩ (I
B
= 0.1mA)
1/t
CLK
= 1MHz
MSTR = 0V
MSTR = V
DD
SPI Inputs and EN Pin at 0V or V
DDS
,
SPI Outputs Unloaded
READY/ACTIVE State
IDLE State
R
BIAS
= 2k to 20k
V
A
≤ 1.6V
V
A
= |V
IP
– V
IM
|
V
TCMP
= A
TCMP
• V
ICMP
V
ICMP
= 0V to V
DD
IDLE State, V
IP
= V
IM
= 0V to V
DD
V
CM
= V
DD
/2 to V
DD
– 0.2V,
V
ICMP
= 0.2V to 1.5V
IP/IM Not Driving
Single-Ended to IP or IM
t
DWELL
= 240ns
V
WAKE
= 240mV
l
l
l
l
l
l
4.8
7
2
2.4
2
1
Voltage on IBIAS Pin
Isolated Interface Bias Current (Note 6)
Isolated Interface Current Gain
Transmitter Pulse Amplitude
l
l
1.9
I
B
= 1mA
I
B
= 0.1mA
V
DD
< 3.3V
V
DD
≥ 3.3V
l
l
l
l
l
l
l
l
18
18
2.0
0
V
BIAS
/R
BIAS
20
20
Threshold-Setting Voltage on ICMP Pin
Leakage Current on ICMP Pin
Leakage Current on IP and IM Pins
Receiver Comparator Threshold Voltage
Gain
Receiver Common Mode Bias
V
CM
Receiver Input Resistance
R
IN
Idle/Wake-Up (See Figures 13, 14, 15)
Differential Wake-Up Voltage
V
WAKE
(See Figure 13)
Dwell Time at V
WAKE
t
DWELL
Start-Up Time After Wake Detection
t
READY
Idle Time-Out Duration
t
IDLE
Digital I/O
V
IH(CFG)
Digital Voltage Input High, Configuration
Pins (PHA, POL, MSTR, SLOW)
Digital Voltage Input Low, Configuration
V
IL(CFG)
Pins (PHA, POL, MSTR, SLOW)
Digital Voltage Input High, SPI Pins
V
IH(SPI)
(CS, SCK, MOSI, MISO)
Digital Voltage Input Low, SPI Pins
V
IL(SPI)
(CS, SCK, MOSI, MISO)
Digital Voltage Input High, EN Pin
V
IH(EN)
V
IL(EN)
V
OH
V
OL
Digital Voltage Input Low, EN Pin
Digital Voltage Output High (CS and SCK)
Digital Voltage Output Low
(MOSI, MISO,
CS,
SCK)
0.2
0.4
0.5
V
V
mA
22
mA/mA
24
mA/mA
V
DD
– 1.7V
V
1.6
V
1.5
V
±1
µA
±2
µA
0.6
V/V
V
kΩ
mV
ns
µs
ms
V
0.3 • V
DD
V
V
V
V
V
V
V
V
V
V
V
V
V
6820f
2.1
l
(V
DD
– V
ICMP
/3 – 167mV)
26
35
42
240
240
4
0.7 • V
DD
5.7
8
7.5
l
l
l
l
V
DD
= 2.7V to 5.5V (POL, PHA, MSTR, SLOW)
V
DD
= 2.7V to 5.5V (POL, PHA, MSTR, SLOW)
V
DDS
= 2.7V to 5.5V
V
DDS
= 1.7V to 2.7V
V
DDS
= 2.7V to 5.5V
V
DDS
= 1.7V to 2.7V
V
DDS
= 2.7V to 5.5V
V
DDS
= 1.7V to 2.7V
V
DDS
= 2.7V to 5.5V
V
DDS
= 1.7V to 2.7V
V
DDS
= 3.3V, Sourcing 2mA
V
DDS
= 1.7V, Sourcing 1mA
V
DDS
= 3.3V, Sinking 3.3mA
V
DDS
= 1.7V, Sinking 1mA
l
l
l
0.7 • V
DDS
l
0.8 • V
DDS
l
l
l
2
l
0.85 • V
DDS
l
l
l
V
DDS
– 0.2
l
V
DDS
– 0.25
l
l
0.3 • V
DDS
0.2 • V
DDS
0.8
0.25 • V
DDS
0.2
0.2
3
LTC6820
The
l
denotes the specifications which apply over the full specified
junction temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= 2.7V to 5.5V, V
DDS
= 1.7V to 5.5V, R
BIAS
= 2k to 20k
unless otherwise specified. All voltages are with respect to GND.
SYMBOL PARAMETER
I
LEAK(DIG)
Digital Pin Input Leakage Current
Input/Output Pin Capacitance
C
I/O
Isolated Pulse Timing (See Figure 2)
t
1/2PW(CS)
Chip-Select Half-Pulse Width
Chip-Select Pulse Inversion Delay
t
INV(CS)
Chip-Select Response Delay
t
DEL(CS)
Data Half-Pulse Width
t
½PW(D)
Data Pulse Inversion Delay
t
INV(D)
Data Response Delay
t
DEL(D)
isoSPI™ Timing—Master (See Figures 3, 4)
SCK Latching Edge to SCK Latching Edge
t
CLK
MOSI Setup Time Before SCK Latching Edge
t
1
MOSI Hold Time After SCK Latching Edge
t
2
SCK Low
t
3
SCK High
t
4
CS
Rising Edge to
CS
Falling Edge
t
5
SCK Latching Edge to
CS
Rising Edge
t
6
CS
Falling Edge to SCK Latch Edge
t
7
SCK Non-Latch Edge to MISO Valid
t
8
SCK Latching Edge to Short ±1 Transmit
t
9
CS
Transition to Long ±1 Transmit
t
10
CS
Rising Edge to MISO Rising
t
11
isoSPI Timing—Slave (See Figures 3, 4)
isoSPI Data Recognized to SCK
t
12
Latching Edge
SCK Pulse Width
t
13
t
14
t
15
t
16
t
17
t
18
t
RTN
CONDITIONS
PHA, POL, MSTR, SLOW = 0V to V
DD
CS,
SCK, MOSI, MISO, EN = 0V to V
DDS
(Note 9)
MIN
l
elecTrical characTerisTics
TYP
MAX
±1
10
UNITS
µA
pF
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
µs
ns
µs
ns
µs
ns
µs
ns
µs
ns
µs
ns
ns
µs
l
l
l
l
l
120
150
140
50
75
40
(Note 8)
(Note 7)
(Note 8)
t
CLK
= t
3
+ t
4
≥ 1µs
t
CLK
= t
3
+ t
4
≥ 1µs
(Note 7)
(Note 7)
(Note 8)
SLOW = 0
SLOW = 1
l
180
200
190
60
70
120
l
l
l
l
l
l
l
l
l
l
l
l
1
5
25
25
50
50
0.6
1
1
55
50
55
55
110
0.9
90
0.9
115
0.9
90
0.9
200
1.8
90
0.9
145
1.1
115
1.1
145
1.1
120
1.1
265
2.2
120
1.1
485
3.3
185
1.4
150
1.4
190
1.4
160
1.4
345
2.8
160
1.4
35
625
4
(Note 8)
(Note 8)
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
SLOW = 0
SLOW = 1
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
l
SCK Non-Latch Edge to isoSPI Data Transmit (Note 8)
CS
Falling Edge to SCK Non-Latch Edge
CS
Falling Edge to isoSPI Data Transmit
CS
Rising Edge to SCK Latching Edge
CS
Rising Edge to MOSI Rising Edge
Data Return Delay
PHA = 1
PHA = 1
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All currents into pins are positive, and all voltages are referenced
to GND unless otherwise specified.
Note 3:
The LTC6820I is guaranteed to meet specified performance
from –40°C to 85°C. The LTC6820H is guaranteed to meet specified
performance from –40°C to 125°C.
Note 4:
Active supply current (I
DD
) is dependent on the amount of time
that the output drivers are active on IP and IM. During those times I
DD
will
increase by the 20 • I
B
drive current. For the maximum data rate 1MHz,
the drivers are active approximately 10% of the time if MSTR = 1, and 5%
6820f
4
LTC6820
elecTrical characTerisTics
of the time if MSTR = 0. See Applications Information section for more
detailed information.
Note 5:
The IO supply pin, V
DDS
, provides power for the SPI inputs and
outputs, including the EN pin. If the inputs are near 0V or V
DDS
(to avoid
static current in input buffers) and the outputs are not sourcing current,
then I
DDS
includes only leakage current.
Note 6:
The LTC6820 is guaranteed to meet specifications with R
BIAS
resistor values ranging from 2k to 20k, with 1% or better tolerance. Those
resistor values correspond to a typical I
B
that can range from 0.1mA
(for 20k) to 1mA (for 2k).
Note 7:
These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT-5 cable (which has a velocity of propagation
of 66% the speed of light). Use of longer cables would require derating
these specs by the amount of additional delay.
Note 8:
These specifications do not include rise or fall time. While fall
time (typically 5ns due to the internal pull-down transistor) is not a
concern, rising-edge transition time t
RISE
is dependent on the pull-up
resistance and load capacitance. In particular, t
12
and t
14
require t
RISE
< 110ns (if SLOW = 0) for the slave’s setup and hold times. Therefore,
the recommended time constant is 50ns or less. For example, if the
total capacitance on the data pin is 25pF (including self capacitance
C
I/O
of 10pF), the required pull-up resistor value is R
能源基础设施
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
