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AN-9735
Design Guideline for LED Lamp Control Using Primary-
Side Regulated Flyback Converter, FAN103 & FSEZ1317
Introduction
Many LED lamp systems use the flyback converter
topology. In applications where precise output current
regulation is required, current sensing in the secondary side
is always necessary, which results in additional sensing loss.
For power supply designers struggling to meet increasing
regulatory pressures, the output current sensing is a daunting
design challenge.
Primary-Side Regulation (PSR) for power supplies can be
an optimal solution for compliance and cost in LED lamp
systems. Primary-side regulation controls the output voltage
and current precisely with information in the primary side of
the LED lamp controller only. This removes the output
current sensing loss and eliminates all secondary-feedback
circuitry. This facilitates a higher efficiency power supply
design without incurring tremendous costs. Fairchild
Semiconductor PWM PSR controller FAN103 and Fairchild
Power Switch (FPS™) (MOSFET + Controller, EZ-PSR)
FSEZ1317 significantly simplify meeting tighter efficiency
requirements with fewer external components.
This application note presents design considerations for
LED lamp systems employing Fairchild Semiconductor
components. It includes designing the transformer and
output filter, selecting the components, and implementing
constant-current control. The step-by-step procedure
completes a power supply design. The design is verified
through an experimental prototype converter using
FSEZ1317. Figure 1 shows the typical application circuit
for an LED lamp using FSEZ1317.
Figure 1. Typical Application Circuit
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
www.fairchildsemi.com
AN-9735
APPLICATION NOTE
Operation Principle of Primary-Side
Regulation
Figure 2 shows typical waveforms of a flyback converter.
Generally, Discontinuous Conduction Mode (DCM)
operation is preferred for primary-side regulation since it
allows better output regulation. The key of primary-side
regulation is how to obtain output voltage and current
information without directly sensing them. Once these
values are obtained, the control can be accomplished by the
conventional feedback compensation method.
Stage I
I
PK
Stage II
Stage III
Stage I
current (I
F
) decreases linearly from the peak value to zero.
At the end of t
DIS
, all the energy stored in the inductor has
been delivered to the output.
Stage III
When the diode current reaches zero, the transformer
auxiliary winding voltage (V
A
) begins to oscillate by the
resonance between the primary-side inductor (L
m
) and the
output capacitor of MOSFET.
Design Procedure
In this section, a design procedure is presented using the
schematic in Figure 3 as a reference.
I
DS
N
N
I
PK
P
S
I
O
= I
F_AVG
I
F
Figure 3. CV & CC Operation Area
V
F
N
A
N
S
[STEP-1] Estimate the Efficiencies
V
O
N
A
N
S
V
A
Figure 3 shows the CV & CC operation area. To optimize
the power stage design, the efficiencies and input powers
should be specified for operating point A (nominal output
voltage and current), B (70% of nominal output voltage),
and C (minimum output voltage).
1.
Estimated overall efficiency (η) for operating points
A, B, and C: The overall power conversion efficiency
should be estimated to calculate the input power. If
no reference data is available, set
η
= 0.7 ~ 0.75 for
low-voltage output applications and
η
= 0.8 ~ 0.85
for high-voltage output applications.
Estimated primary-side efficiency (η
P
) and
secondary-side efficiency (η
S
) for operating points A,
B, and C. Figure 4 shows the definition of primary-
side and secondary-side efficiencies, where the
primary-side efficiency is for the power transfer from
AC line input to the transformer primary side, while
the secondary-side efficiency is for the power transfer
from the transformer primary side to the power
supply output.
t
ON
t
DIS
t
S
Figure 2. Key Waveforms of PSR Flyback Converter
The operation principles of DCM flyback converter are:
Stage I
During the MOSFET ON time (t
ON
), input voltage (V
DL
) is
applied across the primary-side inductor (L
m
). Then
MOSFET current (I
DS
) increases linearly from zero to the
peak value (I
PK
). During this time, the energy is drawn from
the input and stored in the inductor.
Stage II
When the MOSFET is turned off, the energy stored in the
inductor forces the rectifier diode (D
F
) to be turned on.
During the diode conduction time (t
DIS
), the output voltage
(V
O
), together with diode forward-voltage drop (V
F
), are
applied across the secondary-side inductor and the diode
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
2
2.
The typical values for the primary-side and secondary-side
efficiencies are given as:
P
,
S
;
V
O
10
V
1
3
2
3
(1)
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AN-9735
APPLICATION NOTE
P
,
S
;
V
O
10
V
2
3
1
3
(2)
The secondary-side efficiency at 70% of nominal output
voltage (operating point B) can be approximated as:
S
@
B
0.7
V
O
V
V
S
O N F
N
0.7
V
O
V
F
V
O
N
N
(6)
Then, the power supply input power and transformer input
power at 70% nominal output voltage (operating point B)
are given as:
P
IN
@
B
½
0.7
V
O
I
O
N
N
@
B
(7)
N
P
IN
_
T
@
B
½
Figure 4. Primary- and Secondary-Side Efficiency
0.7
V
O
I
O
N
S
@
B
(8)
With the estimated overall efficiency, the input power at
nominal output is given as:
The overall efficiency at the minimum output voltage
(operating point C) can be approximated as:
P
IN
½
V
O
I
O
N
N
@
C
(3)
V
V
min
O N F
V
O
V
F
V
O
V
O
N
min
(9)
where, Vo
min
is the minimum output voltage.
The secondary-side efficiency at minimum output voltage
(operating point C) can be approximated as:
where V
ON
and I
ON
are the nominal output voltage and
current, respectively.
The input power of transformer at nominal output is given
as:
@
C
P
IN
_
T
½
V
O
I
O
N
N
V
V
S
min
O N F
V
O
V
F
V
O
V
O
N
min
(10)
S
(4)
When the output voltage drops below 70% of its nominal
value, the frequency is reduced to 33kHz to prevent CCM
operation. Thus, the transformer should be designed for
DCM both at 70% of nominal output voltage and minimum
output voltage.
As output voltage reduces in CC Mode, the efficiency also
drops. To optimize the transformer design, it is necessary to
estimate the efficiencies properly at 70% of nominal output
voltage and minimum output voltage conditions.
The overall efficiency at 70% of nominal output voltage
(operating point B) can be approximated as:
Then, the power supply input power and transformer input
power at the minimum output voltage (operating point C)
are given as:
P
IN
@
C
½
V
O
min
@
C
min
I
O
N
(11)
N
P
IN
_
T
@
B
½
V
O
S
@
C
I
O
(12)
[STEP-2] Determine the DC Link Capacitor
(C
DL
) and the DC Link Voltage Range
It is typical to select the DC link capacitor as 2-3µF per watt
of input power for universal input range (90 ~ 265V
RMS
) and
1µF per watt of input power for European input range (195
~ 265V
RMS
). With the DC link capacitor chosen, the
minimum DC link voltage is obtained as:
@
B
0.7
V
O
V
V
O N F
N
0.7
V
O
V
F
V
O
N
N
(5)
where V
F
is diode forward-voltage drop.
V
DL
min
½
2
(
V
LINE
min 2
)
P
IN
(1
D
ch
)
C
DL
f
L
(13)
where V
LINEmin
is the minimum line voltage, C
DL
is the
DC link capacitor, f
L
is the line frequency, and D
ch
is the
DC link capacitor charging duty ratio defined as shown in
Figure 5, which is typically about 0.2.
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
www.fairchildsemi.com
3
AN-9735
APPLICATION NOTE
voltage should be also considered. The maximum voltage
stress of MOSFET is given as:
D
ch
T
½
1
T
2
Figure 5. DC Link Voltage Waveforms
V
DS
max
½
V
DL
max
V
RO
V
OS
(20)
The maximum DC link voltage is given as:
For reasonable snubber design, voltage overshoot (V
OS
) is
typically 1~1.5 times the reflected output voltage. It is also
typical to have a margin of 15~20% of breakdown voltage
for maximum MOSFET voltage stress.
(14)
V
DL
max
½
2
V
LINE
max
where V
LINEmax
is the maximum line voltage.
The minimum input DC link voltage at 70% nominal output
voltage are given as:
(
V
O
V
F
)
N
P
N
S
V
DL
@
B
min
½
2
(
V
LINE
min 2
)
P
IN
@
B
(1
D
ch
)
C
DL
f
L
(15)
The minimum input DC link voltage at minimum output
voltage are given as:
Figure 6. Voltage Stress of MOSFET
V
DL
@
C
min
½
2
(
V
LINE
min 2
)
P
IN
@
C
(1
D
ch
)
C
DL
f
L
(16)
[STEP-3] Determine the Transformer Turns
Ratio
Figure 6 shows the MOSFET drain-to-source voltage
waveforms. When the MOSFET is turned off, the sum of
the input voltage (V
DL
) and the output voltage reflected to
the primary is imposed across the MOSFET as:
The transformer turns ratio between the auxiliary winding
and secondary winding (N
A
/N
S
) should be determined by
considering the permissible IC supply voltage (V
DD
) range
and minimum output voltage in constant current. When the
LED operates in constant current, V
DD
is changed, together
with the output voltage, as seen Figure 7. The overshoot of
auxiliary winding voltage caused by the leakage inductance
also affects the V
DD
. V
DD
voltage at light-load condition,
where the overshoot of auxiliary winding voltage is
negligible, is given as:
V
DS
nom
½
V
DL
max
V
RO
(17)
VDD
min 1
½
N
A
V
O
V
F
V
FA
N
S
(21)
where V
RO
is reflected output voltage defined as:
V
RO
½
N
S
V
O
V
F
N
P
(18)
where V
F
is the diode forward voltage drop and N
P
and N
S
are number of turns for the primary side and secondary
side, respectively.
When the MOSFET is turned on, the output voltage,
together with input voltage reflected to the secondary, are
imposed across the diode as:
The actual V
DD
voltage at heavy load is higher than
Equation (21) due to the overshoot by the leakage
inductance, which is proportional to the voltage overshoot
of MOSFET drain-to-source voltage shown in Figure 7.
Considering the effect of voltage overshoot, the V
DD
voltages for nominal output voltage and minimum output
voltage are given as:
VDD
max
VDD
min 2
N
N
A
V
O
V
F
S
V
OS
V
FA
N
S
N
P
N
N
A
min
V
O
V
F
S
V
OS
V
FA
N
S
N
P
(22)
V
F
½
V
O
N
S
max
V
DL
N
P
(23)
(19)
As observed in Equations (5) and (6), increasing the
transformer turns ratio (N
P
/N
S
) results in increased voltage
of MOSFET, while it leads to reduced voltage stress of
rectifier diode. Therefore, the transformer turns ratio
(N
P
/N
S
) should be determined by the compromise between
MOSFET and diode voltage stresses. When determining the
transformer turns ratio, the voltage overshoot (V
OS
) on drain
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
4
where V
FA
is the diode forward-voltage drop of auxiliary
winding diode.
www.fairchildsemi.com
AN-9735
APPLICATION NOTE
Transformer primary-side inductance can be calculated as:
L
m
½
(
V
DL
@
B
min
t
ON
@
B
)
2
f
S
2
P
IN
_
T
@
B
(26)
The maximum peak-drain current can be obtained at the
nominal output condition as:
I
DS
PK
½
2
P
IN
_
T
L
m
f
S
(27)
The MOSFET conduction time at the nominal output
condition is obtained as:
t
ON
½
I
DS
PK
L
m
V
DL
min
(28)
Figure 7. V
DD
and Winding Voltage
The minimum number of turns for the transformer primary
side to avoid the core saturation is given by:
[STEP-4] Design the Transformer
Figure 8 shows the definition of MOSFET conduction time
(t
ON
), diode conduction time (t
DIS
), and non-conduction time
(t
OFF
). The sum of MOSFET conduction time and diode
conduction time at 70% of nominal output voltage is
obtained as:
N
P
min
L
I
½
m DS
B
sat
A
e
PK
(29)
where A
e
is the cross-sectional area of the core in m
2
and
B
sat
is the saturation flux density in Tesla.
Figure 9 shows the typical characteristics of ferrite core
from TDK (PC40). Since the saturation flux density (B
sat
)
decreases as the temperature rises, the high-temperature
characteristics should be considered when it comes to
charger in enclosed case. If there is no reference data, use
B
sat
=0.25~0.3T.
Once the turns ratio is obtained, determine the proper
integer for N
S
so that the resulting N
P
is larger than N
Pmin
obtained from Equation (29).
t
ON
@
B
t
DIS
@
B
min
N
V
DL
@
B
½
t
ON
@
B
1
S
N
P
0.7
V
O
V
F
(24)
The first step in transformer design is to determine how
much non-conduction time (t
OFF
) is allowed in DCM
operation.
Once the t
OFF
is determined, by considering the frequency
variation caused by frequency hopping and its own
tolerance, the MOSFET conduction time is obtained as:
t
ON
@
B
1
t
OFF
@
B
f
S
½
min
V
DL
@
B
N
S
1
N
P
0.7
V
O
V
F
(25)
Figure 8. Definition of t
ON
, t
DIS
, and t
OFF
Figure 9. Typical B-H Curves of Ferrite Core (TDK/PC40)
© 2011 Fairchild Semiconductor Corporation
Rev. 1.0.0 • 4/12/11
www.fairchildsemi.com
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