®
8XC196MH INDUSTRIAL MOTOR CONTROL
CHMOS MICROCONTROLLER
s
High Performance CHMOS 16-bit CPU
s
16 MHz Operating Frequency
s
32 Kbytes of On-chip OTPROM/ROM
s
744 Bytes of On-chip Register RAM
s
Register-to-register Architecture
s
16 Prioritized Interrupt Sources
s
Peripheral Transaction Server (PTS) with 15
Prioritized Sources
s
Up to 52 I/O Lines
s
3-phase Complementary Waveform Generator
s
8-channel 8- or 10-bit A/D with Sample and
Hold
s
2-channel UART
s
Event Processor Array (EPA) with 2 High-
speed Capture/Compare Modules and 4 High-
speed Compare-only Modules
s
Two Programmable 16-bit Timers with
Quadrature Counting Inputs
s
Two Pulse-width Modulator (PWM) Outputs
with High Drive Capability
s
Flexible 8- or 16-bit External Bus
s
1.75
µs
16
×
16 Multiply
s
3
µs
32/16 Divide
s
Extended Temperature Available
s
Idle and Powerdown Modes
s
Watchdog Timer
The 8XC196MH is a member of Intel’s family of 16-bit MCS
®
96 microcontrollers. It is designed primarily to
control three-phase AC induction and DC brushless motors. It features an enhanced three-phase waveform
generator specifically designed for use in “inverter” motor-control applications. This peripheral provides pulse-
width modulation and three-phase sine wave generation with minimal CPU intervention. It generates three
complementary non-overlapping PWM pulses with resolutions of 0.125
µs
(edge triggered) or 0.250
µs
(centered).
The 8XC196MH has two dedicated serial port peripherals, allowing less software overhead. The watchdog timer
can be programmed with one of four time options.
The 8XC196MH is available as the 80C196MH, which does not have on-chip ROM, the 87C196MH,
which contains 32 Kbytes of on-chip OTPROM* or factory programmed ROM, and the 83C196MH, which
contains 32 Kbytes of factory programmed MASK ROM. It is available in 84-lead PLCC, 80-lead Shrink EIAJ/QFP,
and 64-lead SDIP. The 64-lead package does not contain pins for the P5.1/INST and P6.7/PWM1 signals.
Operational characteristics are guaranteed over the temperature range of
– 40°C to
+
85°C
.
*One-Time Programmable Read-Only Memory (OTPROM) is similar to EPROM but comes in an unwindowed package and
cannot be erased. It is user programmable.
Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent
licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.
©
INTEL CORPORATION, 2002
May 2002
Order Number: 272543-002
®
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
the application. The Intel
Packaging
Handbook (order
number 240800) describes Intel’s thermal impedance
test methodology.
Table 1. Thermal Characteristics
Package Type
84-lead PLCC
80-lead QFP
64-lead SDIP
θ
JA
33°C/W
56°C/W
56°C/W
θ
JC
11°C/W
12°C/W
N/A
PROCESS INFORMATION
This device is manufactured on PX29.5, a CHMOS IV
process. Additional process and reliability information
is available in Intel’s
Components Quality and
Reliability
Handbook (order number 210997).
All thermal impedance data is approximate for static
air conditions at 1 watt of power dissipation. Values
will change depending on operating conditions and
X XX 8 X C 196 XX XX
Device Speed:
Product Family:
No Mark = 16 MHz
Kx, Mx, Nx
CHMOS Technology
Program Memory Options:
Package - Type Options:
Temperature and Burn In Options:
0 = ROMless, 3 = ROM, 7 = OTPROM
D = SDIP, N = PLCC, S = QFP
No Mark = –40˚C – +85˚C Ambient
with Intel Standard Burn-In
A2759-01
Figure 2. The 8XC196MH Family Nomenclature
3
8XC196MH INDUSTRIAL MOTOR CONTROL CHMOS MICROCONTROLLER
®
Table 2. 8XC196MH Memory Map
Address
(1)
0FFFFH
0A000H
09FFFH
02080H
0207FH
0205EH
0205DH
02040H
0203FH
02030H
0202FH
02020H
0201FH
0201CH
0201BH
0201AH
02019H
02018H
02017H
02014H
02013H
02000H
01FFFH
01F00H
1EFFH
300H
2FFH
18H
17H
00H
External Memory
Internal ROM/OTPROM or External Memory
Reserved
PTS Vectors
Interrupt Vectors (upper)
ROM/OTPROM Security Key
Reserved
Reserved (must contain 20H)
CCB1
Reserved (must contain 20H)
CCB0
Reserved
Interrupt Vectors (lower)
Internal SFRs
External Memory
Register RAM
CPU SFRs
3
1
1
1, 2
1, 2
Description
Notes
NOTES:
1. Unless otherwise noted, write 0FFH to reserved memory locations and write 0 to reserved SFR bits.
2.
WARNING:
The contents and/or function of reserved locations may change with future revisions of the
device.
3. Code executed in locations 0000H to 02FFH will be forced external.
4
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