PHD9NQ20T
N-channel TrenchMOS standard level FET
Rev. 03 — 16 December 2010
Product data sheet
1. Product profile
1.1 General description
Standard level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Higher operating power due to low
thermal resistance
Low conduction losses due to low
on-state resistance
Suitable for high frequency
applications due to fast switching
characteristics
1.3 Applications
DC-to-DC converters
General purpose switching
Motor control circuits
Off-line switched-mode power
supplies
TV and computer monitor power
supplies
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
gate-drain charge
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
mb
= 25 °C; V
GS
= 10 V
T
mb
= 25 °C
V
GS
= 10 V; I
D
= 4.5 A;
T
j
= 25 °C
V
GS
= 10 V; I
D
= 9 A;
V
DS
= 160 V; T
j
= 25 °C
Min
-
-
-
-
Typ
-
-
-
300
Max Unit
200
8.7
88
400
V
A
W
mΩ
Static characteristics
Dynamic characteristics
Q
GD
-
12
-
nC
NXP Semiconductors
PHD9NQ20T
N-channel TrenchMOS standard level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
[1]
source
mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
2
1
3
SOT428 (DPAK)
[1]
It is not possible to make connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
PHD9NQ20T
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
Version
SOT428
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
non-repetitive avalanche current
T
mb
= 25 °C
pulsed; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 7.2 A;
V
sup
≤
25 V; unclamped; t
p
= 100 µs;
R
GS
= 50
Ω
V
sup
≤
25 V; V
GS
= 10 V; T
j(init)
= 25 °C;
R
GS
= 50
Ω;
unclamped
V
GS
= 10 V; T
mb
= 100 °C
V
GS
= 10 V; T
mb
= 25 °C
pulsed; T
mb
= 25 °C
T
mb
= 25 °C
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
Min
-
-
-30
-
-
-
-
-55
-55
-
-
-
Max
200
200
30
6.2
8.7
35
88
175
175
8.7
35
93
Unit
V
V
V
A
A
A
W
°C
°C
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
I
AS
-
8.7
A
PHD9NQ20T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 December 2010
2 of 12
NXP Semiconductors
PHD9NQ20T
N-channel TrenchMOS standard level FET
100
P
der
(%)
80
003aae674
100
I
D
(%)
80
003aae675
60
60
40
40
20
20
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized total power dissipation as a
function of mounting base temperature
003aae676
Fig 2.
Normalized continuous drain current as a
function of mounting base temperature
10
003aae688
10
3
I
DM
(A)
10
2
R
DS(on)
= V
DS
/ I
D
tp = 10
μs
100
μs
l
AS
(A)
T
j
prior to avalanche = 150
°C
25
°C
1
D.C.
10
1 ms
10 ms
100 ms
1
1
10
10
2
V
DS
(V)
10
3
10
−1
10
−3
10
−2
10
−1
1
t
AV
(ms)
10
T
mb
= 25 °C; I
DM
is single pulse
Fig 3.
Safe operating area; continuous and peak drain
currents as a function of drain-source voltage
Fig 4.
unclamped inductive load
Single-shot avalanche rating; avalanche
current as a function of avalanche period
PHD9NQ20T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 December 2010
3 of 12
NXP Semiconductors
PHD9NQ20T
N-channel TrenchMOS standard level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from
junction to mounting base
thermal resistance from
junction to ambient
mounted on printed-circuit board ;
minimum footprint
Conditions
Min
-
-
Typ
-
50
Max
1.7
-
Unit
K/W
K/W
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
003aae677
0.2
10
−1
0.1
0.05
0.02
single pulse
10
−2
10
−6
10
−5
10
−4
10
−3
t
p
T
P
δ
=
t
p
T
t
10
−2
10
−1
1
t
p
(s)
Fig 5.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD9NQ20T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 December 2010
4 of 12
NXP Semiconductors
PHD9NQ20T
N-channel TrenchMOS standard level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source breakdown
voltage
gate-source threshold
voltage
Conditions
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 0.25 mA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 200 V; V
GS
= 0 V; T
j
= 175 °C
V
DS
= 200 V; V
GS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -10 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 4.5 A; T
j
= 175 °C
V
GS
= 10 V; I
D
= 4.5 A; T
j
= 25 °C
I
D
= 9 A; V
DS
= 160 V; V
GS
= 10 V;
T
j
= 25 °C
Min
200
178
1
2
-
-
-
-
-
-
-
-
-
-
V
DS
= 25 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C
-
-
-
V
DS
= 100 V; R
L
= 10
Ω;
V
GS
= 10 V;
R
G(ext)
= 5.6
Ω;
T
j
= 25 °C
-
-
-
-
V
DS
= 25 V; I
D
= 4.5 A; T
j
= 25 °C
from tab to centre of die ; T
j
= 25 °C
From source lead to source bond pad ;
T
j
= 25 °C
I
S
= 9 A; V
GS
= 0 V; T
j
= 25 °C
I
S
= 9 A; dI
S
/dt = -100 A/µs;
V
GS
= -10 V; V
DS
= 25 V; T
j
= 25 °C
3.8
-
-
Typ
-
-
-
3
-
-
0.05
10
10
-
300
24
4
12
959
93
54
8
19
25
15
6
3.5
7.5
Max
-
-
-
4
6
500
10
100
100
1.16
400
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
V
V
V
V
V
µA
µA
nA
nA
Ω
mΩ
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
S
nH
nH
Static characteristics
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
g
fs
L
D
L
S
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
transfer conductance
internal drain inductance
internal source inductance
Source-drain diode
V
SD
t
rr
Q
r
source-drain voltage
reverse recovery time
recovered charge
-
-
-
0.85
92
0.5
1.2
-
-
V
ns
µC
PHD9NQ20T
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 03 — 16 December 2010
5 of 12
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