Features
H
PowerPC single issue integer core.
H
Precise exception model.
H
Extensive system development support
- on-chip watchpoints and breakpoints,
- program flow tracking,
- On-chip emulation (OnCE) development interface.
H
High performance (Dhrystone 2.1: 52 MIPS @ 50 MHz, 3.3V, 1.3 Watts total power).
H
Low power (< 241 mW @25 MHz, 2.4 V internal, 3.3 V I/O-core, caches, MMUs, I/O).
H
MPC8XX PowerPC system interface, including a periodic interrupt timer, a bus monitor, and
real-time clocks.
H
Single Issue, 32-Bit Version of the Embedded PowerPC Core (fully Compatible with Book 1 of
the PowerPC Architecture Definition) with 32 X 32 – Bit Fixed Point Registers
– Embedded PowerPC Performs Branch Folding, Branch Prediction with Conditional Prefetch,
without Conditional Execution
– 4 Kbyte Data Cache and 4 Kbyte Instruction Cache, Each with an MMU
– Instruction and Data Caches are two way, Set Associative, Physical Address, 4 Word Line
Burst, Least Recently Used (LRU) Replacement, Lockable On-Line Granularity
– MMUs with 32 Entry TLB, Fully associative Instruction and Data TLBs
– MMUs Support Multiple Page Sizes of 4kB, 16 kB, 256 KB, 512 KB and 8 MB ; 16 Virtual
Address Spaces and 8 Protection Groups
– Advanced On-Chip-Emulation Debug Mode
H
Up to 32-bit Data Bus
(Dynamic Bus Sizing for 8 and 16 bits).
H
32 Address Lines
H
Fully Static Design.
H
V
CC
= +3.3 V± 5 % .
H
f
max
= 66 MHz (80 MHZ tbc)
TSPC860
32 BIT QUAD INTEGRATED
POWER QUICC
TM
COMMUNICATION
CONTROLLER
PRELIMINARY
SPECIFICATION
beta SITE
H
Military temperature range : –55°C < T
C
< +125°C.
H
P
D
= 0.75 W typical @ 66 MHz
H
ATM SAR support available on TSPC860SR version
Description
The TSPC860 PowerPCt QUad Integrated Communication Controller (Power
QUICCt)
is a
versatile one-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications. It particularly excels in communications and networking sys-
tems. The Power QUICC (pronounced ”quick”) can be described as a PowerPC-based derivative
of TS68EN360 (QUICCt).
The CPU on the TSPC860 is a 32-bit PowerPC implementation that incorporates memory man-
agement units (MMUs) and instruction and data caches. The communications processor module
(CPM) of the TS68EN360 QUICC has been enhanced with the addition of the interprocessor-inte-
grated controller (I
2
C) channel. Moderate to high digital signal processing (DSP) functionality has
been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 to
support any type of memory, including high performance memories and newer dynamic random
access memories (DRAMs). Overall system functionality is completed with the addition of a
PCMCIA socket controller supporting up to two sockets and a real-time clock.
PBGA 357
ZP suffix
Screening / Quality
This product will be manufactured in full compliance with :
H
Or according to ATMEL-Grenoble standard.
August 2000
1/96
SUMMARY
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . 3
1. MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. PIN ASSIGNEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1. Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
5.8. Ethernet Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.9. I2C AC Electrical Specifications SCL < 100 KHz . . . . . . . . . . . . 83
5.10. SPI Master AC Electrical Specifications . . . . . . . . . . . . . . . . . . . 84
5.11. SPI Slave AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . 86
5.12. I2C AC Electrical Specifications SCL < 100 KHz . . . . . . . . . . . 88
5.13. I2C AC Electrical Specifications SCL > 100 KHz . . . . . . . . . . . 89
5.6. SCC In NMSI Mode External Clock Electrical Specifications . . 75
5.7. SCC In NMSI Mode Internal Clock Electrical Specifications . . 76
3. SIGNALS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1. System Bus Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2. Active Pull up Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3. Internal Pull Up and Pull Down Resistors . . . . . . . . . . . . . . . . . . 26
3.4. Recommended Basic Pin Connections . . . . . . . . . . . . . . . . . . . . . 27
3.4.1. Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.3.1.1.Reset Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.2. JTAG and Debug Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.3. Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.4.4. Unused Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5. Signal States during Hardware Reset . . . . . . . . . . . . . . . . . . . . . . 27
6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . . . . . . . 90
6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
B. DETAILED SPECIFICATIONS . . . . . . . . . . . . . . 29
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . . . . . . 29
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2. Design and construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.1. Terminal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.2. Lead material and finish . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.3. Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.5. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2. Certificate of compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7. POWER CONSIDERATION . . . . . . . . . . . . . . . . . . . . . . . 90
8. LAYOUT PRACTICES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9. FUNCTIONAL UNITS DESCRIPTION . . . . . . . . . . . . . . 90
9.1. Embedded PowerPC Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.2. System Interface Unit (SIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.2.1. PCMCIA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
9.2.2. Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.2.3. Communications Processor Module (CPM) . . . . . . . . . . . . . . . 92
9.3. Software Compatibility Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.4. TSPC860 PowerQUICC Glueless System Design . . . . . . . . . . . . 93
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . 30
4.1. General requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.2. DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.3. AC Electrical Specifications Control Timing . . . . . . . . . . . . . . . . 33
4.4. IEEE 1149.1 ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . 60
10. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11. PACKAGE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 94
11.1. Plastic Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5. CPM ELECTRICAL CHARACTERISTICS . . . . . . . . . . . 63
5.1. PIP/PIO AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . 63
5.2. IDMA Controller AC Electrical Specifications . . . . . . . . . . . . . . 66
5.3. Baud Rate Generator AC Electrical Specifications . . . . . . . . . . . 69
5.4. Timer AC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . 70
5.5. Serial Interface AC Electrical Specifications . . . . . . . . . . . . . . . . 71
12. DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
13. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . 96
2/96
TSPC860
TSPC860
A. GENERAL DESCRIPTION
The TSPC860 is functionally composed of three major blocks :
H
A 32-bit PowerPC core with MMUs and caches
H
A system interface unit
H
A communications processor module
Figure 1 : Block diagram view of the TSPC860
1. MAIN FEATURES
The following is a list of the TSPC860’s important features:
H
Fully static design
H
Four major power saving modes
H
357 OMPAC ball grid array packaging (plastic)
H
32-bit address and data busses
H
Flexible memory management
H
4-kbyte physical address, two-way, set-associative data cache
H
4-kbyte physical address, two-way, set-associative instruction cache
H
Eight-bank memory controller
- Glueless interface to SRAM, DRAM, EPROM, FLASH and other peripherals
- Byte write enables and selectable parity generation
- 32-bit address decodes with bit masks
3/96
H
System interface unit-
- Clock synthesizer-
- Power management-
- Reset controller-
- PowerPC decrementer and time base-
- Real-time clock register-
- Periodic interrupt timer-
- Hardware bus monitor and software watchdog timer-
- IEEE 1149.1 JTAG test access port
H
Communications processor module
- Embedded 32-bit RISC controller architecture for flexible I/O
- Interfaces to PowerPC core through on-chip dual-port RAM and virtual DMA channel controller
- Continuous mode transmission and reception on all serial channels
- Serial DMA channels for reception and transmission on all serial channels
- I/O registers with open-drain and interrupt capability
- Memory-memory and memory-I/O transfers with virtual DMA functionality
-
Protocols
supported by ROM or downloadable microcode and include, but limited to, the digital portion of :
D
Ethernet / IEEE 802.3 CS/CDMA
D
HDLC2 / SDLC and HDLC bus
D
Apple talk
D
Signaling system #7 (RAM microcode only)
D
Universal asynchronous receiver transmitter (UART)
D
Synchronous UART
D
Binary synchronous (BiSync) communications
D
Totally transparent
D
Totally transparent with CRC
D
Profibus (RAM microcode option)
D
Asynchronous HDLC
D
DDCMP
D
V.14 (RAM microcode option)
D
X.21 (RAM microcode option)
D
V.32bis datapump filters
D
IrDA serial infrared
D
Basis rate ISDN (BRI) in conjunction with SMC channels
D
Primary rate ISDN (MH version only)
- Four hardware serial communications controller channels supporting the protocols
- Two hardware serial management channels
D
Management for BRI devices as general circuit interface controller multiplexed channels
D
low-speed UART operation
- Hardware serial peripheral interfaces
- I
2
C (microwire compatible) interface
- Time-slot assigner
- Port supports Centronics interfaces anc chip-to-chip
- Four independent baud rate generators and four input clock pins for supplying clocks to SMC and SCC serial channels
- Four independant 16-bit timers which can be interconnected as two 32-bit timers
4/96
TSPC860
TSPC860
2. PIN ASSIGNEMENT
2.1. Plastic Ball Grid Array
TOP VIEW
Figure 2 : Pin Assignment
3. SIGNALS DESCRIPTION
This section describes the signals on the TSPC860.
5/96
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
