MOTOROLA
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by MC68340/D
SEMICONDUCTOR
PRODUCT INFORMATION
MC68340
MC68340V
Product Brief
Integrated Processor
With
DMA
The MC68340 is a high-performance 32-bit integrated processor with direct memory access (DMA),
combining an enhanced M68000-compatible processor, 32-bit DMA, and other peripheral subsystems on a
single integrated circuit. The MC68340 CPU32 delivers 32-bit CISC processor performance from a lower
cost 16-bit memory system. The combination of peripherals offered in the MC68340 can be found in a
diverse range of microprocessor-based systems, including embedded control and general computing.
Systems requiring very high-speed block transfers of data can especially benefit from the MC68340's DMA.
The MC68340's high level of functional integration results in significant reductions in component count,
power consumption, board space, and cost while yielding much higher system reliability and shorter design
time. The 3.3-V MC68340V is particularly attractive to applications requiring a very tight power budget.
Complete code compatibility with the MC68000 affords the designer access to a broad base of established
real-time kernels, operating systems, languages, applications, and development tools—many oriented
towards embedded control. Figure 1 shows a block diagram of the MC68340.
SYSTEM
INTEGRATION
MODULE
SYSTEM
PROTECTION
CPU32
CORE
TWO-
CHANNEL
SERIAL
I/O
32
CLOCK
16
EXTERNAL
BUS
INTERFACE
BUS
ARBITRATION
INTERMODULE BUS
IEEE TEST
TWO-CHANNEL DMA
CONTROLLER
TIMER
MODULE
TIMER
MODULE
Figure 1. MC68340 Simplified Block Diagram
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
© MOTOROLA INC.,
1992
Rev 3
Also Replaces BR752/D
The primary features of the MC68340 are as follows:
• High Functional Integration on a Single Piece of Silicon
• CPU32—MC68020-Derived 32-Bit Central Processor Unit
— Upward Object-Code Compatible with MC68000 and MC68010
— Additional 32-Bit MC68020 Instructions and Addressing Modes
— Unique Embedded Control Instructions
— Fast Two-Clock Register Instructions—10,045 Dhrystones/Second
• Two-Channel Low-Latency DMA Controller for High-Speed Memory Transfers
— Single- or Dual-Address Transfers
— 32-Bit Addresses and Counters
— 8-, 16-, and 32-Bit Data Transfers
— 50 Mbyte/Sec Sustained Transfers (12.5 Mbyte/Sec Memory-to-Memory)
• Two-Channel Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
— Baud Rate Generators
— Modem Control
— MC68681/MC2681 Compatible
— 9.8 Mbits/Sec Maximum Transfer Rate
• Two Independent Counter/Timers
— 16-Bit Counter
— Up to 8-Bit Prescaler
— Multimode Operation
— 80-ns Resolution
• System Integration Module Incorporates Many Functions Typically Relegated to
External PALs, TTL, and ASIC, such as:
— System Configuration
— External Bus Interface
— System Protection
— Periodic Interrupt Timer
— Chip Select and Wait State Generation
— Interrupt Response
— Clock Generation
— Bus Arbitration
— Dynamic Bus Sizing
— IEEE 1149.1 Boundary Scan (JTAG)
— Up to 16 Discrete I/O Lines
— Power-On Reset
32 Address Lines, 16 Data Lines
Power Consumption Control
— Static HCMOS Technology Reduces Power in Normal Operation
— Low Voltage Operation at 3.3 V
±0.3
V (MC68340V only)
— Programmable Clock Generator Throttles Frequency
— Unused Peripherals Can Be Turned Off
— LPSTOP Provides an Idle State for Lowest Standby Current
0–16.78 MHz or 0–25.16 MHz Operation
144-Pin Ceramic Quad Flat Pack (CQFP) or 145-Pin Plastic Pin Grid Array (PGA)
•
•
•
•
As a low voltage part, the MC68340V can operate with a 3.3-V power supply. MC68340 is used throughout
this document to refer to both the low voltage and standard 5-V parts since both are functionally equivalent.
2
MC68340 PRODUCT INFORMATION
MOTOROLA
M68300 FAMILY
The MC68340 is one of a series of components in Motorola's M68300 Family. Other members of the family
include the MC68302, MC68330, MC68331, MC68332, and MC68F333.
ORGANIZATION
The M68300 family of integrated processors and controllers is built on an M68000 core processor, an on-
chip bus, and a selection of intelligent peripherals appropriate for a set of applications. The CPU32 is a
powerful central processor with nearly the performance of the MC68020. A system integration module
incorporates the external bus interface and many of the smaller circuits that typically surround a
microprocessor for address decoding, wait-state insertion, interrupt prioritization, clock generation,
arbitration, watchdog timing, and power-on reset timing.
Each member of the M68300 family is distinguished by its selection of peripherals. Peripherals are chosen
to address specific applications but are often useful in a wide variety of applications. The peripherals may be
highly sophisticated timing or protocol engines that have their own processors, or they may be more
traditional peripheral functions, such as UARTs and timers. Since each major function is designed in a
standalone module, each module might be found in many different M68300 family parts. Driver software
written for a module on one M68300 part can be used to run the same module that appears on another part.
ADVANTAGES
By incorporating so many major features into a single M68300 family chip, a system designer can realize
significant savings in design time, power consumption, cost, board space, pin count, and programming. The
equivalent functionality can easily require 20 separate components. Each component might have 16–64
pins, totaling over 350 connections. Most of these connections require interconnects or are duplications.
Each connection is a candidate for a bad solder joint or misrouted trace. Each component is another part to
qualify, purchase, inventory, and maintain. Each component requires a share of the printed circuit board.
Each component draws power—often to drive large buffers to get the signal to another chip. The cumulative
power consumption of all the components must be available from the power supply. The signals between
the CPU and a peripheral might not be compatible nor run from the same clock, requiring time delays or
other special design considerations.
In a M68300 family component, the major functions and glue logic are all properly connected internally,
timed with the same clock, fully tested, and uniformly documented. Power consumption stays well under a
watt, and a special standby mode drops current well under a milliamp during idle periods. Only essential
signals are brought out to pins. The primary package is the surface-mount quad flat pack for the smallest
possible footprint; pin grid arrays are also available.
MC68340 SIGNALS
Figure 2 shows the components and signals.
MOTOROLA
MC68340 PRODUCT INFORMATION
3
BKPT/DSCLK
TCK
TMS
TDI
TDO
A31/PORT A7/IACK7
A30/PORT A6/IACK6
A29/PORT A5/IACK5
A28/PORT A4/IACK4
A27/PORT A3/IACK3
A26/PORT A2/IACK2
A25/PORT A1/IACK1
A24/PORT A0
FREEZE
IPIPE/DS0
IFETCH/DS1
PORT A
SCLK
X2
X1
CPU32
68020-BASED
PROCESSOR
A23–A0
D15–D0
FC3–FC0
RESET
BERR
HALT
AS
DS
R/W
SIZ1
SIZ0
DSACK1
DSACK0
BR
BG
BGACK
RMC
TEST
TWO-CHANNEL
SERIAL
I/O
RxDA
TxDA
CTSA
RxDB
TxDB
CTSB
EXTERNAL
BUS
INTERFACE
OUTPUT
PORT
SYSTEM
INTEGRATION
MODULE
(SIM40)
TxRDYA/OP6
RxRDYA/FFULLA/OP4
RTSB/OP1
RTSA/OP0
IMB
BUS
ARBITRATION
CLOCK
TWO-CHANNEL DMA
CONTROLLER
EXTAL
XTAL
TIMER
MODULE
TIMER
MODULE
IRQ7/PORT B7
IRQ6/PORT B6
IRQ5/PORT B5
IRQ3/PORT B3
CS3/IRQ4/PORT B4
CS2/IRQ2/PORT B2
CS1/IRQ1/PORT B1
CS0/AVEC
MODCK/PORT B0
PORT B
DREQ1
DACK1
DONE1
DREQ2
DACK2
DONE2
TGATE1
TIN1
TOUT1
TGATE2
TIN2
TOUT2
Figure 2. MC68340 Detailed Block Diagram
4
MC68340 PRODUCT INFORMATION
CLKOUT
XFC
MOTOROLA
CENTRAL PROCESSOR UNIT
The CPU32 is a powerful central processor that supervises system functions, makes decisions, manipulates
data, and directs I/O. A special debugging mode simplifies processor emulation during system debug.
CPU32
The CPU32 is an M68000 family processor specially designed for use as a 32-bit core processor and for
operation over the intermodule bus (IMB). Designers used the MC68020 as a model and included advances
of the later M68000 family processors, resulting in an instruction execution performance of 4 MIPS (VAX-
equivalent) at 25.16 MHz.
The powerful and flexible M68000 architecture is the basis of the CPU32. MC68000 (including the
MC68HC000 and the MC68EC000) and MC68010 user programs will run unmodified on the CPU32. The
programmer can use any of the eight 32-bit data registers for fast manipulation of data and any of the eight
32-bit address registers for indexing data in memory. The CPU32 can operate on data types of single bits,
binary-coded decimal (BCD) digits, and 8, 16, and 32 bits. Peripherals and data in memory can reside
anywhere in the 4-Gbyte linear address space. A supervisor operating mode protects system-level
resources from the more restricted user mode, allowing a true virtual environment to be developed.
Flexible instructions for data movement, arithmetic functions, logical operations, shifts and rotates, bit set
and clear, conditional and unconditional program branches, and overall system control are supported,
including a fast 32
×
32 multiply and 32-bit conditional branches. Instructions, such as table lookup and
interpolate and low power stop, support specific requirements of embedded control applications. Many
addressing modes complement these instructions, including predecrement and postincrement, which allow
simple stack and queue maintenance and scaled indexed for efficient table accesses. Data types and
addressing modes are supported orthogonally by all data operations and with all appropriate addressing
modes. Position-independent code is easily written.
The CPU32 is specially optimized to run with the MC68340's 16-bit data bus. Most instructions execute in
one-half the number of clocks compared to the original MC68000, yielding an overall 1.6 times the
performance of the same-speed MC68000 and measuring 10,045 Dhrystones/sec @ 25.16 MHz
(6,742 Dhrystones/sec @ 16.78 MHz).
Like all M68000 family processors, the CPU32 recognizes interrupts of seven different priority levels and
allows the peripheral to vector the processor to the desired service routine. Internal trap exceptions ensure
proper instruction execution with good addresses and data, allow operating system intervention in special
situations, and permit instruction tracing. Hardware signals can either terminate or rerun bad memory
accesses before instructions process data incorrectly.
The CPU32 offers the programmer full 32-bit data processing performance with complete M68000
compatibility, yet with more compact code than is available with RISC processors. The CPU32 is identical in
all CPU32-based M68300 family products.
BACKGROUND DEBUG MODE
A special operating mode is available in the CPU32 in which normal instruction execution is suspended
while special on-chip microcode performs the functions of a debugger. Commands are received over a
dedicated, high-speed, full-duplex serial interface. Commands allow the manual reading or writing of CPU32
registers, reading or writing of external memory locations, and diversion to user-specified patch code. This
background debug mode permits a much simpler emulation environment while leaving the processor chip in
the target system, running its own debugging operations.
MOTOROLA
MC68340 PRODUCT INFORMATION
5
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