CYRF69303
Programmable Radio-on-Chip LPstar
Programmable Radio-on-Chip LPstar
Features
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Operating temperature from 0 °C to 70 °C
Closed-loop frequency synthesis for minimal frequency drift
Radio System-on-Chip with built-in 8-bit MCU in a single
device.
Operates in the unlicensed worldwide Industrial, Scientific, and
Medical (ISM) band (2.400 GHz to 2.483 GHz).
On Air compatible with second
WirelessUSB™ LP and PRoC LP.
generation
radio
Simple Development
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Auto transaction sequencer (ATS): MCU can remain in sleep
state longer to save power
Framing, length, CRC16, and Auto ACK
Separate 16 byte transmit and receive FIFOs
Receive signal strength indication (RSSI)
Built-in serial peripheral interface (SPI) control while in Sleep
Mode
Advanced development tools based on Cypress’s PSoC
®
tools
Flexible I/O
2 mA source current on all GPIO pins. Configurable 8 mA or
50 mA/pin current sink on designated pins
Each GPIO pin supports high impedance inputs, configurable
pull up, open drain output, CMOS/TTL inputs, and CMOS
output
Maskable interrupts on all I/O pins
Pin-to-pin compatible with PRoC LP except the pin 31 and
pin 37.
Intelligent
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M8C based 8-bit CPU, optimized for human interface devices
(HID) applications
256 bytes of SRAM
8 Kbytes of flash memory with EEPROM emulation
In-system reprogrammable through D+/D– pins
CPU speed up to 12 MHz
16-bit free running timer
Low power wakeup timer
12-bit programmable interval timer with interrupts
Watchdog timer
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BOM Savings
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Low external component count
Small footprint 40-pin QFN (6 mm × 6 mm)
GPIOs that require no external components
Operates off a single crystal
Low Power
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21 mA operating current (Transmit at –5 dBm)
Sleep current less than 1
A
Operating voltage from 2.7 V to 3.6 V DC
Fast startup and fast channel changes
Supports coin cell operated applications
Applications
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Wireless keyboards and mice
Presentation tools
Wireless gamepads
Remote controls
Toys
Fitness
Reliable & Robust
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Receive sensitivity typical –90 dBm
AutoRate™ - Dynamic Data Rate Reception
❐
Enables data reception for any of the supported bit rates
automatically.
❐
DSSS (250 Kbps), GFSK (1 Mbps)
Cypress Semiconductor Corporation
Document Number: 001-66502 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised April 27, 2013
CYRF69303
Logic Block Diagram
MOSI
SCK
nSS
V
CC
V
CC
V
Bat1
V
Bat2
V
Bat0
V
CC4
V
CC3
V
CC2
V
DD_MICRO
V
CC1
Vdd
RST
RFbias
RFp
RFn
Microcontroller
Function
P0_1,3,4,7
4
P1_0:2,6:7
5
P2_0:1
GND
Radio
Function
IRQ/GPIO
MISO/GPIO
XOUT/GPIO
P1.5/MOSI
P1.4/SCK
P1.3/nSS
RESV
GND
.....
12 MHz
.......
Document Number: 001-66502 Rev. *D
GND
Xtal
2
V
IO
Page 2 of 70
CYRF69303
Contents
Functional Description ..................................................... 4
Functional Overview ........................................................ 4
2.4 GHz Radio Function .............................................. 4
Data Transmission Modes ........................................... 4
Microcontroller Function .............................................. 4
Backward Compatibility ............................................... 4
Pinouts .............................................................................. 5
Pin Definitions .................................................................. 5
Functional Block Overview .............................................. 6
2.4 GHz Radio ............................................................. 6
Frequency Synthesizer ................................................ 6
Baseband and Framer ................................................. 6
Packet Buffers and Radio Configuration Registers ..... 7
Auto Transaction Sequencer (ATS) ............................ 7
Interrupts ..................................................................... 7
Clocks .......................................................................... 8
GPIO Interface ............................................................ 8
Power-on Reset ........................................................... 8
Timers ......................................................................... 8
Power Management .................................................... 8
Low Noise Amplifier (LNA) and
Received Signal Strength Indication (RSSI) ....................... 9
SPI Interface ...................................................................... 9
Three-Wire SPI Interface ............................................. 9
Four-Wire SPI Interface ............................................... 9
SPI Communication and Transactions ...................... 10
SPI I/O Voltage References ...................................... 10
SPI Connects to External Devices ............................ 10
CPU Architecture ............................................................ 11
CPU Registers ................................................................. 11
Flags Register ........................................................... 11
Accumulator Register ................................................ 12
Index Register ........................................................... 12
Stack Pointer Register ............................................... 12
CPU Program Counter High Register ....................... 12
CPU Program Counter Low Register ........................ 12
Addressing Modes ......................................................... 13
Source Immediate ..................................................... 13
Source Direct ............................................................. 13
Source Indexed ......................................................... 13
Destination Direct ...................................................... 13
Destination Indexed ................................................... 14
Destination Direct Source Immediate ........................ 14
Destination Indexed Source Immediate .................... 14
Destination Direct Source Direct ............................... 14
Source Indirect Post Increment ................................. 15
Destination Indirect Post Increment .......................... 15
Instruction Set Summary ............................................... 16
Memory Organization ..................................................... 17
Flash Program Memory Organization ....................... 17
Data Memory Organization ....................................... 18
Flash .......................................................................... 18
SROM ........................................................................ 18
SROM Function Descriptions .................................... 19
Clocking .......................................................................... 22
SROM Table Read Description ................................. 23
Clock Architecture Description .................................. 24
CPU Clock During Sleep Mode ................................. 28
Reset ................................................................................ 29
Power-on Reset ......................................................... 30
Watchdog Timer Reset .............................................. 30
Sleep Mode ...................................................................... 30
Sleep Sequence ........................................................ 30
Low Power in Sleep Mode ......................................... 31
Wakeup Sequence .................................................... 31
Power-on Reset Control ................................................. 32
POR Compare State ................................................. 33
ECO Trim Register .................................................... 33
General-Purpose I/O Ports ............................................. 33
Port Data Registers ................................................... 33
GPIO Port Configuration ........................................... 35
GPIO Configurations for Low Power Mode ............... 41
Serial Peripheral Interface (SPI) ................................ 42
SPI Data Register ...................................................... 43
SPI Configure Register .............................................. 43
SPI Interface Pins ...................................................... 45
Timer Registers .............................................................. 45
Registers ................................................................... 45
Interrupt Controller ......................................................... 48
Architectural Description ........................................... 48
Interrupt Processing .................................................. 49
Interrupt Latency ....................................................... 49
Interrupt Registers ..................................................... 49
Microcontroller Function Register Summary ............. 54
Radio Function Register Summary ............................... 56
Absolute Maximum Ratings .......................................... 57
DC Characteristics ......................................................... 57
AC Characteristics ......................................................... 59
Switching Waveforms .................................................... 60
RF Characteristics .......................................................... 63
Ordering Information ...................................................... 65
Ordering Code Definitions ......................................... 65
Package Handling ........................................................... 66
Package Diagrams .......................................................... 66
Acronyms ........................................................................ 68
Document Conventions ................................................. 68
Units of Measure ....................................................... 68
Document History Page ................................................. 69
Sales, Solutions, and Legal Information ...................... 70
Worldwide Sales and Design Support ....................... 70
Products .................................................................... 70
PSoC Solutions ......................................................... 70
Document Number: 001-66502 Rev. *D
Page 3 of 70
CYRF69303
Functional Description
PRoC LPstar devices are integrated radio and microcontroller
functions in the same package to provide a dual-role single-chip
solution.
Communication between the microcontroller and the radio is
through the radio’s SPI interface.
Data Transmission Modes
The radio supports two different data transmission modes:
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In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS
In DSSS mode eight bits (8DR, 32 chip) are encoded in each
derived code symbol transmitted, resulting in effective 250 kbps
data rate.
Functional Overview
The CYRF69303 is a complete Radio System-on-Chip device,
providing a complete RF system solution with a single device and
a few discrete components. The CYRF69303 is designed to
implement low-cost wireless systems operating in the worldwide
2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band
(2.400 GHz to 2.4835 GHz).
32 chip Pseudo Noise (PN) codes are supported. The two data
transmission modes apply to the data after the SOP. In particular
the length, data, and CRC16 are all sent in the same mode. In
general, DSSS reduce packet error rate in any environment.
Microcontroller Function
The MCU function is an 8-bit Flash-programmable
microcontroller. The instruction set is optimized specifically for
HID and a variety of other embedded applications.
The MCU function has up to 8 Kbytes of Flash for user’s code
and up to 256 bytes of RAM for stack space and user variables.
In addition, the MCU function includes a Watchdog timer, a
vectored interrupt controller, a 16-bit Free Running Timer, and
12-bit Programmable Interrupt Timer.
The microcontroller has 15 GPIO pins grouped into multiple
ports. With the exception of the four radio function GPIOs, each
GPIO port supports high impedance inputs, configurable pull-up,
open drain output, CMOS/TTL inputs and CMOS output. Up to
two pins support programmable drive strength of up to 50 mA.
Additionally, each I/O pin can be used to generate a GPIO
interrupt to the microcontroller. Each GPIO port has its own GPIO
interrupt vector with the exception of GPIO Port 0. GPIO Port 0
has two dedicated pins that have independent interrupt vectors
(P0.3 - P0.4).
The microcontroller features an internal oscillator.
2.4 GHz Radio Function
The SoC contains a 2.4 GHz, 1 Mbps GFSK radio transceiver,
packet data buffering, packet framer, DSSS baseband controller,
received signal strength indication (RSSI), and SPI interface for
data transfer and device configuration.
The radio supports 98 discrete 1 MHz channels (regulations may
limit the use of some of these channels in certain jurisdictions).
The baseband performs DSSS spreading/despreading, Start of
Packet (SOP), End of Packet (EOP) detection, and CRC16
generation and checking. The baseband may also be configured
to automatically transmit Acknowledge (ACK) handshake
packets whenever a valid packet is received.
When in receive mode, with packet framing enabled, the device
is always ready to receive data transmitted at any of the
supported bit rates. This enables the implementation of
mixed-rate systems in which different devices use different data
rates. This also enables the implementation of dynamic data rate
systems that use high data rates at shorter distances or in a
low-moderate interference environment or both. It changes to
lower data rates at longer distances or in high interference
environments or both.
Backward Compatibility
The CYRF69303 IC is fully interoperable with the main modes of
the second generation Cypress radio SoC namely the
CYRF6936, CYRF69103 and CYRF69213.
CYRF69303 IC device may transmit data to or receive data from
a second generation device, or both.
Document Number: 001-66502 Rev. *D
Page 4 of 70
CYRF69303
Pinouts
Figure 1. 40-pin QFN pinout
V
DD_1.8
36
V
BAT0
39
GND 37
P0.7 38
P1.7 35
P1.6 32
RST 34
Vcc 40
NC 31
Corner
tabs
V
IO
33
P0.4
XTAL
V
CC
P0.3
P0.1
V
BAT1
V
CC
P2.1
V
BAT2
1
2
3
4
5
6
7
8
9
* E-PAD Bottom Side
30 XOUT / GPIO
29 MISO / GPIO
28 P1.5 / MOSI
27 IRQ / GPIO
CYRF69303
PRoC LPstar
26 P1.4 / SCK
25 P1.3 / SS
24 P1.2
23 V
DD_Micro
22 P1.1
21 P1.0
RF
BIAS
10
11 RF
P
12 GND
13 RF
N
14 NC
15 P2.0
16 V
CC
17 NC
18 NC
19 RESV
20 NC
Pin Definitions
Pin
1
2
3, 7, 16, 40
4
5
6
8
9
10
11
12
13
14, 17, 18, 20
15
19
21
22
23
24
25
26
Name
P0.4
XTAL
V
CC
P0.3
P0.1
V
bat1
P2.1
V
bat2
RF
bias
RF
p
GND
RF
n
NC
P2.0
RESV
GPIO
Reserved. Must connect to GND
Individually configured GPIO
12 MHz crystal
Connected to 2.7 V to 3.6 V supply, through 0.047
F
bypass C.
Individually configured GPIO
Individually configured GPIO
Connect to 2.7 V to 3.6 V power supply, through 47 ohm series/1
F
shunt C
GPIO. Port 2 Bit 1
Connected to 2.7 V to 3.6 V main power supply, through 0.047
F
bypass C
RF pin voltage reference
Differential RF to or from antenna
GND
Differential RF to or from antenna
Description
P1.0 /
GPIO 1.0 / ISSP-SCLK
ISSP-SCLK
P1.1 /
GPIO 1.1 / ISSP-SDATA
ISSP-SDATA
V
DD_micro
P1.2
P1.3 / nSS
P1.4 / SCK
MCU supply connected to V
CC
, max CPU 12 MHz
GPIO
Slave Select
SPI Clock
Document Number: 001-66502 Rev. *D
Page 5 of 70
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