CY8C23433, CY8C23533
PSoC
®
Programmable System-on-Chip™
Features
■
Powerful Harvard-architecture processor
❐
M8C processor speeds to 24 MHz
❐
8x8 multiply, 32-bit accumulate
❐
Low power at high speed
❐
3.0 V to 5.25 V operating voltage
❐
Industrial temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC blocks)
❐
Four Rail-to-Rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 8-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
❐
Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• CRC and PRS modules
• Full-duplex UART
• Multiple SPI masters or slaves
• Connectable to all GPIO Pins
❐
Complex peripherals by combining blocks
❐
High-Speed 8-Bit SAR ADC optimized for motor control
Precision, programmable clocking
❐
Internal ±2.5% 24/48 MHz oscillator
❐
High accuracy 24 MHz with optional 32 KHz crystal and PLL
❐
Optional external oscillator, up to 24 MHz
❐
Internal oscillator for watchdog and sleep
Flexible on-chip memory
❐
8K bytes flash program storage 50,000 erase/write cycles
❐
256 bytes SRAM data storage
❐
In-system serial programming (ISSP)
❐
Partial flash updates
❐
Flexible protection modes
❐
EEPROM emulation in flash
Programmable pin configurations
❐
25 mA Sink, 10 mA source on all GPIO
❐
Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
❐
Up to eight analog inputs on GPIO plus two additional analog
inputs with restricted routing
❐
Two 30 mA analog outputs on GPIO
❐
Configurable interrupt on all GPIO
Additional system resources
2
❐
I C slave, master, and multi-master to 400 kHz
❐
Watchdog and sleep timers
❐
User-configurable low voltage detection
❐
Integrated supervisory circuit
❐
On-chip precision voltage reference
■
Complete development tools
❐
Free development software (PSoC Designer™)
❐
Full-featured in-circuit emulator and programmer
❐
Full speed emulation
❐
Complex breakpoint structure
❐
128 KB trace memory
■
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Interrupt
Controller
Global Analog Interconnect
Flash 8K
Sleep and
Watchdog
SROM
CPUCore (M8C)
■
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
1 Row
4 Blocks
ANALOG SYSTEM
Analog
Block Array
2 Columns
4 Blocks
Analog
Ref
■
SAR8 ADC
Analog
Input
Muxing
■
Digital
Clocks
Multiply
Accum.
Decimator
I
2
C
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
■
Cypress Semiconductor Corporation
Document Number: 001-44369 Rev. *G
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 8, 2013
CY8C23433, CY8C23533
Contents
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ................................................................... 3
Analog System .................................................................. 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pinouts .............................................................................. 9
32-Pin Part Pinout ....................................................... 9
28-Pin Part Pinout .................................................... 10
Register Reference ......................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 15
Operating Temperature ............................................ 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 31
Packaging Information ................................................... 41
Thermal Impedances ................................................ 42
Capacitance on Crystal Pins .................................... 42
Solder Reflow Peak Temperature ............................. 42
Ordering Information ...................................................... 43
Acronyms ........................................................................ 44
Acronyms Used ......................................................... 44
Reference Documents .................................................... 44
Document Conventions ................................................. 45
Units of Measure ....................................................... 45
Numeric Conventions .................................................... 45
Glossary .......................................................................... 46
Silicon Errata for the CY8C23433, CY8C23533
PSoC® Programmable System-on-Chip ....................... 51
Part Numbers Affected .............................................. 51
CY8C23433 Qualification Status ............................... 51
CY8C23433 Errata Summary .................................... 51
Document History Page ................................................. 52
Sales, Solutions, and Legal Information ...................... 53
Worldwide Sales and Design Support ....................... 53
Products .................................................................... 53
PSoC Solutions ......................................................... 53
Document Number: 001-44369 Rev. *G
Page 2 of 53
CY8C23433, CY8C23533
PSoC Functional Overview
The PSoC family consists of many programmable
system-on-chips with on-chip controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with a low-cost single-chip programmable device.
PSoC devices include configurable blocks of analog and digital
logic, and programmable interconnects. This architecture make
it possible for you to create customized peripheral configurations
that match the requirements of each individual application.
additionally, a fast central processing unit (CPU), flash memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts and packages.
The PSoC architecture, as shown in the
Logic Block Diagram
on
page 1, consists of four main areas: PSoC core, digital system,
analog system, and system resources. Configurable global
busing allows combining all of the device resources into a
complete custom system. The PSoC CY8C23x33 family can
have up to three I/O ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
four analog blocks.
Digital System
The Digital system consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references.
Figure 1. Digital System Block Diagram
Port 3
Port 2
Port 1
Port 0
Digital Clocks
FromCore
To System Bus
ToAnalog
System
DIGITAL SYSTEM
Digital PSoC Block Array
Row Input
Configuration
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
8
8
Row Output
Configuration
PSoC Core
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general Purpose I/O (GPIO)
The M8C CPU core is a powerful processor with speeds up to 24
MHz, providing a four million instructions per second MIPS 8-bit
Harvard-architecture microprocessor. The CPU uses an
interrupt controller with 11 vectors, to simplify programming of
real time embedded events. program execution is timed and
protected using the included sleep and watch dog timers (WDT).
Memory encompasses 8 KB of flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the flash. Program flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
±2.5% over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz internal low speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■
■
■
■
■
■
■
■
■
■
PWMs (8-and 16-bit)
PWMs with Dead band (8- and 16-bit)
Counters (8- to 32- bit)
Timers (8- to 32- bit)
UART 8 bit with selectable parity (up to 1)
Serial peripheral interface (SPI) master and slave (up to 1)
I
2
C slave and multi master (1 available as a system resource)
Cyclical redundancy checker (CRC)/Generator (8 to 32 bit)
IrDA (up to 1)
Pseudo Random Sequence Generators (8- to 32- bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table titled
PSoC Device Character-
istics
on page 5.
Document Number: 001-44369 Rev. *G
Page 3 of 53
CY8C23433, CY8C23533
Analog System
The analog system consists of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Each analog block consists of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
■
■
■
■
■
■
■
■
■
■
■
■
■
Figure 2. Analog System Block Diagram
P0[7]
P0[5]
P0[3]
P0[1]
AGNDIn RefIn
P0[6]
P0[4]
P0[2]
P0[0]
P2[6]
P2[3]
P2[4]
P2[2]
P2[0]
P2[1]
Filters (2 band pass, low-pass)
Amplifiers (up to 2, with selectable gain to 48x)
Instrumentation amplifiers (1 with selectable gain to 93x)
Comparators (1, with 16 selectable thresholds)
Array Input Configuration
DAC (6 or 9-bit DAC)
Multiplying DAC (6 or 9-bit DAC)
High current output drivers (two with 30 mA drive)
1.3-V reference (as a system resource)
DTMF dialer
Modulators
Correlators
Peak detectors
Many other topologies possible
P0[7:0]
ACI2[3:0]
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ACB01
ASD11
ASC21
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks. The Analog column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
8-Bit SAR ADC
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Notes
1. One complete column, plus one Continuous Time Block.
2. Limited analog functionality
.
3. Two analog blocks and one CapSense.
Document Number: 001-44369 Rev. *G
Page 4 of 53
CY8C23433, CY8C23533
Additional System Resources
System resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, decimator,
low voltage detection, and power-on-reset. Brief statements
describing the merits of each system resource follow:
■
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of delta
sigma ADCs.
The I
2
C module provides 100- and 400-kHz communication
over two wires. Slave, master, and multi-master modes are all
supported.
Low-Voltage detection interrupts can signal the application of
falling voltage levels, while the advanced POR circuit
eliminates the need for a system supervisor.
An internal 1.3-V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
■
■
■
PSoC Device Characteristics
Depending on the PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3
analog blocks. Table 1 lists the resources available for specific PSoC device groups.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66
CY8C28xxx
CY8C27x43
CY8C24x94
CY8C24x23A
CY8C23x33
CY8C24x33
CY8C22x45
CY8C21x45
CY8C21x34
CY8C21x23
CY8C20x34
CY8C20xx6
Digital
I/O
up to 64
up to 44
up to 44
up to 56
up to 24
up to 26
up to 26
up to 38
up to 24
up to 28
up to 16
up to 28
up to 36
Digital
Rows
4
up to 3
2
1
1
1
1
2
1
1
1
0
0
Digital
Blocks
16
up to 12
8
4
4
4
4
8
4
4
4
0
0
Analog
Inputs
up to 12
up to 44
up to 12
up to 48
up to 12
up to 12
up to 12
up to 38
up to 24
up to 28
up to 8
up to 28
up to 36
Analog
Outputs
4
up to 4
4
2
2
2
2
0
0
0
0
0
0
Analog
Columns
4
up to 6
4
2
2
2
2
4
4
2
2
0
0
Analog
Blocks
12
up to
12 + 4
[1]
12
6
6
4
4
6
[1]
[1]
SRAM
Size
2K
1K
256
1K
256
256
256
1K
512
512
256
512
up to
2K
Flash
Size
32 K
16 K
16 K
16 K
4K
8K
8K
16 K
8K
8K
4K
8K
up to
32 K
SAR
ADC
No
Yes
No
No
No
Yes
Yes
No
Yes
No
No
No
No
6
4
[1]
4
[1]
3
[1,2]
3
[1,2]
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense
®
.
Document Number: 001-44369 Rev. *G
Page 5 of 53
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