1.8 V Programmable CapSense Controller
with SmartSense™ Auto-tuning
1–33 Buttons, 0–6 Sliders
1.8 V Programmable CapSense
®
Controller with SmartSense™ Auto-tuning 1–33 Buttons, 0–6 Sliders
CY8C20XX6A/S
®
Features
■
■
Low power CapSense
®
block with SmartSense Auto-tuning
❐
Patented CSA_EMC, CSD sensing algorithms
❐
SmartSense_EMC Auto-Tuning
• Sets and maintains optimal sensor performance during run
time
• Eliminates system tuning during development and
production
• Compensates for variations in manufacturing process Low
average power consumption – 28 µA/sensor in run time
(wake-up and scan once every 125 ms)
Powerful Harvard-architecture processor
❐
M8C CPU with a max speed of 24 MHz
Operating Range: 1.71 V to 5.5 V
❐
Standby Mode 1.1
μA
(Typ)
❐
Deep Sleep 0.1
μA
(Typ)
Operating Temperature range: –40 °C to +85 °C
Flexible on-chip memory
❐
8 KB flash, 1 KB SRAM
❐
16 KB flash, 2 KB SRAM
❐
32 KB flash, 2 KB SRAM
❐
Read while Write with EEPROM emulation
❐
50,000 flash erase/write cycles
❐
In-system programming simplifies manufacturing process
Four Clock Sources
❐
Internal main oscillator (IMO): 6/12/24 MHz
❐
Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐
External 32 KHz Crystal Oscillator
❐
External Clock Input
Programmable pin configurations
❐
Up to 36 general-purpose I/Os (GPIOs) configurable as
buttons or sliders
❐
Dual mode GPIO (Analog inputs and Digital I/O supported)
❐
High sink current of 25 mA per GPIO
• Max sink current 120 mA for all GPIOs
❐
Source Current
• 5 mA on ports 0 and 1
• 1 mA on ports 2,3 and 4
❐
Configurable internal pull-up, high-Z and open drain modes
❐
Selectable, regulated digital I/O on port 1
❐
Configurable input threshold on port 1
Versatile Analog functions
❐
Internal analog bus supports connection of multiple sensors
to form ganged proximity sensor
❐
Internal Low-Dropout voltage regulator for high power supply
rejection ratio (PSRR)
Full-Speed USB
❐
12 Mbps USB 2.0 compliant
Additional system resources
❐
I2C Slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐
Configurable up to 12 MHz SPI master and slave
❐
Three 16-bit timers
❐
Watchdog and sleep timers
❐
Integrated supervisory circuit
❐
10-bit incremental analog-to-digital converter (ADC) with
internal voltage reference
❐
Two general-purpose high speed, low power analog
comparators
Complete development tools
❐
Free development tool (PSoC Designer™)
Sensor and Package options
❐
10 Sensors – QFN 16, 24
❐
16 Sensors – QFN 24
❐
22 / 25 Sensors – QFN 32
❐
24 Sensors - WLCSP 30
❐
31 Sensors – SSOP 48
❐
33 Sensors – QFN 48
■
■
■
■
■
■
■
■
■
■
Errata:
For information on silicon errata, see
“Errata”
on page 46. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 001-54459 Rev. *Y
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 18, 2017
CY8C20XX6A/S
Logic Block Diagram
1.8/2.5/3V
LDO
PWRSYS
[1]
(Regulator)
Port 4
Port 3
Port 2
Port 1
Port 0
PSoC CORE
SYSTEM BUS
Global Analog Interconnect
1K/2K
SRAM
Interrupt
Controller
Supervisory ROM (SROM)
8K/16K/32K Flash
Nonvolatile Memory
Sleep and
Watchdog
CPU Core (M8C)
6/12/24 MHz Internal Main Oscillator
(IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE
SYSTEM
Two
Comparators
CapSense
Module
Analog
Reference
Analog
Mux
SYSTEM BUS
USB
I2C
Slave
Internal
Voltage
References
System
Resets
POR
and
LVD
SPI
Master/
Slave
Three 16-Bit
Programmable
Timers
Digital
Clocks
SYSTEM RESOURCES
Note
1. Internal voltage regulator for internal circuitry
Document Number: 001-54459 Rev. *Y
Page 2 of 53
CY8C20XX6A/S
More Information
Cypress provides a wealth of data at
www.cypress.com
to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA92181, Resources Available for CapSense® Controllers.
Following is an abbreviated list for CapSense devices:
■
■
■
Overview:
CapSense Portfolio, CapSense Roadmap
Product Selectors:
CapSense, CapSense Plus, CapSense
Express, PSoC3 with CapSense, PSoC5 with CapSense,
PSoC4.
In addition,
PSoC Designer
offers a device selection
tool at the time of creating a new project.
Application notes: Cypress offers CapSense application notes
covering a broad range of topics, from basic to advanced level.
Recommended application notes for getting started with
CapSense are:
❐
AN64846:
Getting Started With CapSense
®
❐
AN73034:
CY8C20xx6A/H/AS CapSense Design Guide
❐
AN2397:
CapSense® Data Viewing Tools
Technical Reference Manual (TRM):
❐
PSoC® CY8C20xx6A/AS/L Family Technical Reference
Manual
■
Development Kits:
❐
CY3280-20x66 Universal CapSense Controller Kit
features
a predefined control circuitry and plug-in hardware to make
prototyping and debugging easy. Programming and
I2C-to-USB Bridge hardware are included for tuning and data
acquisition.
❐
CY3280-BMM Matrix Button Module Kit
consists of eight
CapSense sensors organized in a 4x4 matrix format to form
16 physical buttons and eight LEDs. This module connects
to any CY3280 Universal CapSense Controller Board,
including CY3280-20x66 Universal CapSense Controller.
❐
CY3280-BSM Simple Button Module Kit
consists of ten
CapSense buttons and ten LEDs. This module connects to
any CY3280 Universal CapSense Controller Board, including
CY3280-20x66 Universal CapSense Controller.
The
CY3217-MiniProg1
and
CY8CKIT-002 PSoC® MiniProg3
device provides an interface for flash programming.
■
PSoC Designer
PSoC Designer
is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of systems based on CapSense (see
Figure 1).
With PSoC Designer, you can:
1. Drag and drop User Modules to build your hardware system
3. Configure User Module
design in the main design workspace
4. Explore the library of user modules
2. Codesign your application firmware with the PSoC hardware,
5. Review user module datasheets
using the PSoC Designer IDE C compiler
Figure 1. PSoC Designer Features
1
3
2
4
5
Document Number: 001-54459 Rev. *Y
Page 3 of 53
CY8C20XX6A/S
Contents
PSoC
®
Functional Overview ............................................ 5
PSoC Core .................................................................. 5
CapSense System ....................................................... 5
Additional System Resources ..................................... 6
Getting Started .................................................................. 7
CapSense Design Guides ........................................... 7
Silicon Errata ............................................................... 7
Development Kits ........................................................ 7
Training ....................................................................... 7
CYPros Consultants .................................................... 7
Solutions Library .......................................................... 7
Technical Support ....................................................... 7
Development Tools .......................................................... 8
PSoC Designer Software Subsystems ........................ 8
Designing with PSoC Designer ....................................... 9
Select User Modules ................................................... 9
Configure User Modules .............................................. 9
Organize and Connect ................................................ 9
Generate, Verify, and Debug ....................................... 9
Pinouts ............................................................................ 10
16-pin QFN (10 Sensing Inputs)[3, 4] ....................... 10
24-pin QFN (17 Sensing Inputs) [8] ........................... 11
24-pin QFN (15 Sensing Inputs (With USB)) [13] ...... 12
30-ball WLCSP (24 Sensing Inputs) [18] ................... 13
32-pin QFN (25 Sensing Inputs) [22] ......................... 14
32-pin QFN (22 Sensing Inputs (With USB)) [27] ...... 15
48-pin SSOP (31 Sensing Inputs) [32] ...................... 16
48-pin QFN (33 Sensing Inputs) [36] ......................... 17
48-pin QFN (33 Sensing Inputs (With USB)) [41] ...... 18
48-pin QFN (OCD) (33 Sensing Inputs) [46] ............. 19
Electrical Specifications ................................................ 20
Absolute Maximum Ratings ....................................... 20
Operating Temperature ............................................. 20
DC Chip-Level Specifications .................................... 21
DC GPIO Specifications ............................................ 22
DC Analog Mux Bus Specifications ........................... 24
DC Low Power Comparator Specifications ............... 24
Comparator User Module
Electrical Specifications .................................................... 25
ADC Electrical Specifications .................................... 25
DC POR and LVD Specifications .............................. 26
DC Programming Specifications ............................... 26
DC I2C Specifications ............................................... 27
DC Reference Buffer Specifications .......................... 27
DC IDAC Specifications ............................................ 27
AC Chip-Level Specifications .................................... 28
AC GPIO Specifications ............................................ 29
AC Comparator Specifications .................................. 30
AC External Clock Specifications .............................. 30
AC Programming Specifications ................................ 31
AC I2C Specifications ................................................ 32
Packaging Information ................................................... 35
Thermal Impedances ................................................. 38
Capacitance on Crystal Pins ..................................... 38
Solder Reflow Specifications ..................................... 38
Development Tool Selection ......................................... 39
Software .................................................................... 39
Development Kits ...................................................... 39
Evaluation Tools ........................................................ 39
Device Programmers ................................................. 39
Accessories (Emulation and Programming) .............. 40
Third Party Tools ....................................................... 40
Build a PSoC Emulator into Your Board .................... 40
Ordering Information ...................................................... 41
Ordering Code Definitions ......................................... 43
Acronyms ........................................................................ 44
Reference Documents .................................................... 44
Document Conventions ................................................. 44
Units of Measure ....................................................... 44
Numeric Naming ........................................................ 45
Glossary .......................................................................... 45
Errata ............................................................................... 46
Qualification Status ................................................... 46
Errata Summary ........................................................ 46
Document History Page ................................................. 49
Sales, Solutions, and Legal Information ...................... 53
Worldwide Sales and Design Support ....................... 53
Products .................................................................... 53
PSoC®Solutions ....................................................... 53
Cypress Developer Community ................................. 53
Technical Support ..................................................... 53
Document Number: 001-54459 Rev. *Y
Page 4 of 53
CY8C20XX6A/S
PSoC
®
Functional Overview
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, Flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as shown in the
Logic
Block Diagram on page 2,
consists of three main areas:
■
■
■
required tuning parameters. SmartSense allows engineers to go
from prototyping to mass production without re-tuning for
manufacturing variations in PCB and/or overlay material
properties.
SmartSense_EMC
In addition to the SmartSense auto tuning algorithm to remove
manual tuning of CapSense applications, SmartSense_EMC
user module incorporates a unique algorithm to improve
robustness of capacitive sensing algorithm/circuit against high
frequency conducted and radiated noise. Every electronic device
must comply with specific limits for radiated and conducted
external noise and these limits are specified by regulatory bodies
(for example, FCC, CE, U/L and so on). A very good PCB layout
design, power supply design and system design is a mandatory
for a product to pass the conducted and radiated noise tests. An
ideal PCB layout, power supply design or system design is not
often possible because of cost and form factor limitations of the
product. SmartSense_EMC with superior noise immunity is well
suited and handy for such applications to pass radiated and
conducted noise test.
Figure 2. CapSense System Block Diagram
CS1
The Core
CapSense Analog System
System Resources (including a full-speed USB port).
A common, versatile bus allows connection between I/O and the
analog system.
Each CY8C20XX6A/S PSoC device includes a dedicated
CapSense block that provides sensing and scanning control
circuitry for capacitive sensing applications. Depending on the
PSoC package, up to 36 GPIO are also included. The GPIO
provides access to the MCU and analog mux.
IDAC
Analog Global Bus
CS2
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit
Harvard-architecture microprocessor.
CSN
Vr
Reference
Buffer
CapSense System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to
33 inputs
[2]
. Capacitive sensing is configurable on each GPIO
pin. Scanning of enabled CapSense pins are completed quickly
and easily across multiple ports.
SmartSense
SmartSense is an innovative solution from Cypress that removes
manual tuning of CapSense applications. This solution is easy to
use and provides a robust noise immunity. It is the only
auto-tuning solution that establishes, monitors, and maintains all
IMO
Cinternal
Comparator
Mux
Mux
Cexternal (P0[1]
or P0[3])
Refs
Cap Sense Counters
CSCLK
CapSense
Clock Select
Oscillator
Note
2. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I
2
C + 1 pin for modulator capacitor.
Document Number: 001-54459 Rev. *Y
Page 5 of 53
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