CY7C65620
CY7C65630
EZ-USB HX2LP™
Low Power USB 2.0 Hub Controller Family
EZ-USB HX2LP™ Low Power USB 2.0 Hub Controller Family
Features
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Integrated upstream and downstream termination resistors
Integrated port status indicator control
24 MHz external crystal (integrated phase-locked loop (PLL))
In-system EEPROM programming
Configurable with external SPI EEPROM:
❐
Vendor ID, Product ID, Device ID (VID/PID/DID)
❐
Number of active ports
❐
Number of removable ports
❐
Maximum power setting for high-speed and full-speed
❐
Hub controller power setting
❐
Power-on timer
❐
Overcurrent detection mode
❐
Enabled and disabled overcurrent timer
❐
Overcurrent pin polarity
❐
Indicator pin polarity
❐
Compound device
❐
Enable full-speed only
❐
Disable port indicators
❐
Ganged power switching
❐
Self and bus powered compatibility
❐
Fully configurable string descriptors for multiple language
support
USB 2.0 hub controller
Automotive and Industrial grade option (–40 °C to 85 °C)
Compliant with USB 2.0 specification
USB-IF certified: TID# 30000009
Windows Hardware Quality Lab (WHQL) Compliant
Up to four downstream ports supported
Supports bus powered and self powered modes
Single transaction translator (TT)
Bus power configurations
Fit, form, and function compatible with CY7C65640 and
CY7C65640A (TetraHub™)
Space saving 56-pin QFN
Single power supply requirement
❐
Internal regulator for reduced cost
Integrated upstream pull-up resistor
Integrated pull-down resistors for all downstream ports
■
■
Block Diagram – CY7C65630
D+
D-
High-Speed
USB Control Logic
SPI Communication
Block
SPI_SCK
SPI_SD
SPI_CS
USB 2.0 PHY
24 MHz
Crystal
PLL
USB Upstream Port
Serial
Interface
Engine
Transaction Translator
Hub Repeater
TT RAM
Routing Logic
USB Downstream Port 1
USB 2.0
PHY
Port Power
Control
Port
Status
USB Downstream Port 2
USB 2.0
PHY
Port Power
Control
Port
Status
USB Downstream Port 3
USB 2.0
PHY
Port Power
Control
Port
Status
USB Downstream Port 4
USB 2.0
PHY
Port Power
Control
Port
Status
D+
D-
PWR#[1]
LED D+
OVR#[1]
D- PWR#[2]
OVR#[2]
LED
D+
D-
PWR#[3]
LED D+
OVR#[3]
D-
PWR#[4]
LED
OVR#[4]
Errata:
For information on silicon errata, see
“Errata”
on page 27. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-08037 Rev. *Z
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 19, 2013
CY7C65620
CY7C65630
Block Diagram – CY7C65620
D+
D-
High-Speed
USB Control Logic
SPI Communication
Block
SPI_SCK
SPI_SD
SPI_CS
USB 2.0 PHY
24 MHz
Crystal
PLL
USB Upstream Port
Serial
Interface
Engine
Transaction Translator (X1)
Hub Repeater
TT RAM
Routing Logic
USB Downstream Port 1
USB 2.0
PHY
Port Power
Control
Port
Status
USB Downstream Port 2
USB 2.0
PHY
Port Power
Control
Port
Status
D+
D- PWR#[1]
OVR#[1]
LED
D+
D-
PWR#[2]
LED
OVR#[2]
Document Number: 38-08037 Rev. *Z
Page 2 of 30
CY7C65620
CY7C65630
Contents
Introduction ....................................................................... 4
USB Serial Interface Engine ........................................ 4
Hub Repeater .............................................................. 4
Transaction Translator ................................................ 4
Applications ...................................................................... 4
Functional Overview ........................................................ 4
System Initialization ..................................................... 4
Enumeration ................................................................ 4
Downstream Ports ....................................................... 5
Upstream Port ............................................................. 5
Power Switching .......................................................... 5
Overcurrent Detection ................................................. 5
Port Indicators ............................................................. 5
Pin Configuration ............................................................. 7
Pin Definitions .................................................................. 8
Default Descriptors ........................................................ 10
Device Descriptor ...................................................... 10
Configuration Descriptor ............................................ 10
Interface Descriptor ................................................... 11
Endpoint Descriptor ................................................... 11
Device Qualifier Descriptor ........................................ 11
Hub Descriptor .......................................................... 12
Configuration Options ................................................... 13
0xD0 Load ................................................................. 13
0xD2 Load ................................................................. 13
0xD4 Load ................................................................. 14
Supported USB Requests .............................................. 17
Device Class Commands .......................................... 17
Hub Class Commands .............................................. 18
Upstream USB Connection ............................................ 20
Downstream USB Connection ....................................... 20
LED Connection .............................................................. 20
System Block Diagram ................................................... 21
Absolute Maximum Ratings .......................................... 22
Operating Conditions ..................................................... 22
Electrical Characteristics ............................................... 22
DC Electrical Characteristics ..................................... 22
USB Transceiver ....................................................... 22
AC Electrical Characteristics ..................................... 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagram ............................................................ 25
Thermal Impedance for the Package ........................ 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Numeric Naming ........................................................ 26
Errata ............................................................................... 27
Part Numbers Affected .............................................. 27
HX2LP Qualification Status ....................................... 27
HX2LP Errata Summary ............................................ 27
Document History Page ................................................. 28
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC Solutions ......................................................... 30
Document Number: 38-08037 Rev. *Z
Page 3 of 30
CY7C65620
CY7C65630
Introduction
EZ-USB HX2LP™ is Cypress’s next generation family of
high-performance, low-power USB 2.0 hub controllers. HX2LP is
an ultra low power single chip USB 2.0 hub controller with
integrated upstream and downstream transceivers, a USB serial
interface engine (SIE), USB hub control and repeater logic, and
TT logic. Cypress has also integrated many of the external
passive components, such as pull-up and pull-down resistors,
reducing the overall bill of materials required to implement a hub
design. The HX2LP portfolio consists of:
■
the route only includes the repeater and no TT, because the
device and the hub are operating at the same speed. When the
hub is operating at full-speed (the upstream port is connected to
a full-speed host controller), a high-speed peripheral does not
operate at its full capability. These devices only work at
full-speed. Full- and low-speed devices connected to this hub
operate at their normal speed.
Applications
Typical applications for the HX2LP device family are:
■
■
■
■
■
■
■
■
CY7C65630: 4-port/single transaction translator
Standalone hubs
Motherboard hubs
Monitor hubs
Advanced port replicators
Docking stations
Split-PC designs
External personal storage drives
Keyboard hubs
This device option is for ultra low-power applications that require
four downstream ports. All four ports share a single transaction
translator. The CY7C65630 is available in 56 QFN and is also
pin-for-pin compatible with the CY7C65640.
■
CY7C65620: 2-port/single transaction translator
This device option is for a 2-port bus powered application. Both
ports share a single transaction translator. The CY7C65620 is
available in a 56 QFN.
All device options are supported by Cypress’s world class
reference design kits, which include board schematics, bill of
materials, Gerber files, Orcad files, and thorough design
documentation.
Functional Overview
The Cypress CY7C65620/CY7C65630 USB 2.0 Hubs are
high-performance, low system cost solutions for USB. The
CY7C65620/CY7C65630 USB 2.0 Hubs integrate 1.5 k
upstream pull-up resistors for full-speed operation and all
downstream 15 k pull-down resistors and series termination
resistors on all upstream and downstream D+ and D– pins. This
results in optimization of system costs by providing built-in
support for the USB 2.0 specification.
USB Serial Interface Engine
The
serial
interface
engine
(SIE)
allows
the
CY7C65620/CY7C65630 to communicate with the USB host.
The SIE handles the following USB activities independently of
the Hub Control Block.
■
■
■
■
Bit stuffing and unstuffing
Checksum generation and checking
TOKEN type identification
Address checking.
System Initialization
On power-up, the CY7C65620/CY7C65630 reads an external
SPI EEPROM for configuration information. At the most basic
level, this EEPROM has the vendor ID (VID), product ID (PID),
and device ID (DID) for the customer’s application. For more
specialized applications, other configuration options can be
specified. See
Configuration Options on page 13
for more
details.
After reading the EEPROM, if VBUSPOWER (connected to
upstream V
BUS
) is high, CY7C65620/CY7C65630 enables the
pull-up resistor on D+ to indicate its presence to the upstream
hub, after which a USB bus reset is expected. During this reset,
CY7C65620/CY7C65630 initiates a chirp to indicate that it is a
high-speed peripheral. In a USB 2.0 system, the upstream hub
responds with a chirp sequence, and CY7C65620/CY7C65630
is in a high-speed mode, with the upstream D+ pull-up resistor
turned off. In USB 1.x systems, no such chirp sequence from the
upstream hub is seen, and CY7C65620/CY7C65630 operates
as a normal 1.x hub (operating at full-speed).
Hub Repeater
The hub repeater manages the connectivity between upstream
and downstream facing ports that are operating at the same
speed. It supports full- or low-speed connectivity and high-speed
connectivity. According to the USB 2.0 specification, the HUB
Repeater provides the following functions:
■
■
Sets up and tears down connectivity on packet boundaries
Ensures orderly entry into and out of the suspend state,
including proper handling of remote wakeups.
Transaction Translator
The TT translates data from one speed to another. A TT takes
high speed split transactions and translates them to full- or
low-speed transactions when the hub is operating at high-speed
(the upstream port is connected to a high-speed host controller)
and has full- or low-speed devices attached. The operating
speed of a device attached on a downstream facing port
determines whether the routing logic connects a port to the TT
or hub repeater. If a full- or low-speed device is connected to the
hub operating at high-speed, the data transfer route includes the
TT. If a high-speed device is connected to this high-speed hub,
Document Number: 38-08037 Rev. *Z
Enumeration
After a USB bus reset, CY7C65620/CY7C65630 is in an
unaddressed, unconfigured state (configuration value set to ’0’).
During the enumeration process, the host sets the hub's address
and configuration. After the hub is configured, the full hub
functionality is available.
Page 4 of 30
CY7C65620
CY7C65630
Downstream Ports
The CY7C65620/CY7C65630 supports a maximum of four
downstream ports, each of which may be marked as usable or
removable in the extended configuration (0xD2 EEPROM load
or 0xD4 EEPROM load, see
Configuration Options on page 13.
Downstream D+ and D– pull-down resistors are incorporated in
CY7C65620/CY7C65630 for each port. Before the hubs are
configured, the ports are driven SE0 (single ended zero, where
both D+ and D– are driven low) and are set to the unpowered
state. When the hub is configured, the ports are not driven and
the host may power the ports by sending a SetPortPower
command for each port. After a port is powered, any connect or
disconnect event is detected by the hub. Any change in the port
state is reported by the hubs back to the host through the status
change endpoint (endpoint 1). On receipt of SetPortReset
request for a port with a device connected, the hub does as
follows:
■
■
■
■
[n]# output pins of the CY7C65620/CY7C65630 series are
connected to the respective external power switch's port power
enable signals. Note that each port power output pin of the
external power switch must be bypassed with an electrolytic or
tantalum capacitor as required by the USB specification. These
capacitors supply the inrush currents, which occur during
downstream device hot-attach events. The polarity of this pin is
configured through the EEPROM; see
Configuration Options on
page 13.
Overcurrent Detection
Overcurrent detection includes 8 ms of timed filtering by default.
This parameter is configured from the external EEPROM in a
range of 0 ms to 15 ms for both enabled ports and disabled ports
individually. Detection of overcurrent on downstream ports is
managed by control pins connected to an external power switch
device.
The OVR[n]# pins of the CY7C65620/CY7C65630 series are
connected to the respective external power switch’s port
overcurrent indication (output) signals. After detecting an
overcurrent condition, hub reports overcurrent condition to the
host and disables the PWR# output to the external power device.
The polarity of the OVR pins can be configured through the
EEPROM; see
Configuration Options on page 13.
Performs a USB reset on the corresponding port
Puts the port in an enabled state
Enables the green port indicator for that port (if not previously
overridden by the host)
Enables babble detection after the port is enabled.
Babble consists of a non-idle condition on the port after EOF2. If
babble is detected on an enabled port, that port is disabled. A
ClearPortEnable request from the host also disables the
specified port.
Downstream ports can be individually suspended by the host
with the SetPortSuspend request. If the hub is not suspended, a
remote wakeup event on that port is reflected to the host through
a port change indication in the hub status change endpoint. If the
hub is suspended, a remote wakeup event on this port is
forwarded to the host. The host may resume the port by sending
a ClearPortSuspend command.
Port Indicators
The USB 2.0 port indicators are also supported directly by
CY7C65620/CY7C65630. According to the specification, each
downstream port of the hub optionally supports a status
indicator. The presence of indicators for downstream facing ports
is specified by bit 7 of the wHubCharacteristics field of the hub
class descriptor. The default CY7C65620/CY7C65630
descriptor specifies that port indicators are supported
(wHubCharacteristics, bit 7 is set). If port indicators are not
included in the hub, disable this bit through EEPROM settings.
Each port indicator pin is strategically located directly on the
opposite edge of the port with which it is associated. A port
indicator provides two colors: green and amber. This is usually
implemented as two separate LEDs, one amber and the other
green. A combination of hardware and software control is used
to inform the user of the current status of the port or the device
attached to the port and to guide the user through problem
resolution. Colors and blinking provide information to the user.
The significance of the color of the LED depends on the
operational
mode
of
CY7C65620/CY7C65630.
The
CY7C65620/CY7C65630 port indicators has two modes of
operation: automatic and manual.
On power up the CY7C65620/CY7C65630 defaults to automatic
mode, where the color of the Port Indicator (green, amber, off)
indicates the functional status of the CY7C65620/CY7C65630
port. In automatic mode, the CY7C65620/CY7C65630 turns on
the green LED whenever the port is enabled and the amber LED
when an overcurrent condition is detected. The color of the port
indicator is set by the port state machine. Blinking of the LEDs is
not supported in automatic mode.
Table 1
identifies the mapping
of color to port state in automatic mode.
Upstream Port
The upstream port includes the transmitter and the receiver state
machine. The transmitter and receiver operate in high-speed
and full-speed depending on the current hub configuration.
The transmitter state machine monitors the upstream facing port
while the hub repeater has connectivity in the upstream direction.
This machine prevents babble and disconnect events on the
downstream facing ports of this hub from propagating and
causing the hub to be disabled or disconnected by the hub to
which it is attached.
Power Switching
The CY7C65620/CY7C65630 includes interface signals for
external port power switches. Both ganged and individual
(per-port) configurations are supported, with individual switching
being the default. Initially all ports are unpowered. After
enumerating, the host may power each port by sending a
SetPortPower request for that port. The power switching and
overcurrent detection of downstream ports is managed by
control pins connected to an external power switch device. PWR
Document Number: 38-08037 Rev. *Z
Page 5 of 30
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
