CY7C1481BV25
72-Mbit (2 M × 36) Flow-Through SRAM
72-Mbit (2 M × 36) Flow-Through SRAM
Features
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Functional Description
The CY7C1481BV25 is a 2.5 V, 2 M × 36 synchronous flow
through SRAM designed to interface with high speed
microprocessors with minimum glue logic. Maximum access
delay from clock rise is 6.5 ns (133 MHz version). A 2-bit on-chip
counter captures the first address in a burst and increments the
address automatically for the rest of the burst access. All
synchronous inputs are gated by registers controlled by a
positive edge triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address pipelining
Chip Enable (CE
1
), depth expansion Chip Enables (CE
2
and
CE
3
), Burst Control inputs (ADSC, ADSP, and ADV), Write
Enables (BW
x
and BWE), and Global Write (GW). Asynchronous
inputs include the Output Enable (OE) and the ZZ pin.
The CY7C1481BV25 enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the Processor
Address Strobe (ADSP) or the cache Controller Address Strobe
(ADSC) inputs. Address advancement is controlled by the
Address Advancement (ADV) input.
Addresses and chip enables are registered at rising edge of
clock when either Address Strobe Processor (ADSP) or Address
Strobe Controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
Advance pin (ADV).
For a complete list of related documentation, click
here.
Supports 133 MHz bus operations
2 M × 36 common I/O
2.5 V core power supply (V
DD
)
2.5 V I/O supply (V
DDQ
)
Fast clock to output time
❐
6.5 ns (133 MHz version)
Provide high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
CY7C1481BV25 available in JEDEC standard Pb-free 100-pin
TQFP package
IEEE 1149.1 JTAG compatible boundary scan
ZZ sleep mode option
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Selection Guide
Description
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
133 MHz
6.5
305
120
Unit
ns
mA
mA
Cypress Semiconductor Corporation
Document Number: 001-74847 Rev. *B
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 18, 2014
CY7C1481BV25
Logic Block Diagram – CY7C1481BV25
A 0, A1, A
ADDRESS
REGISTER
A
[1:0]
MODE
ADV
CLK
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
D
,
DQP
D
BW
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,
DQP
A
BW
A
BWE
GW
CE1
CE2
CE3
OE
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BW
B
BYTE
WRITE REGISTER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP
A
DQP
B
DQP
C
DQP
D
ENABLE
REGISTER
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document Number: 001-74847 Rev. *B
Page 2 of 21
CY7C1481BV25
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC Solutions ......................................................... 21
Document Number: 001-74847 Rev. *B
Page 3 of 21
CY7C1481BV25
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1481BV25
(2 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
MODE
A
A
A
A
A
1
A
0
A
A
V
SS
V
DD
Document Number: 001-74847 Rev. *B
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 4 of 21
CY7C1481BV25
Pin Definitions
Pin Name
A
0
, A
1
, A
I/O
Description
Input-
Address Inputs Used to Select One of the Address Locations.
Sampled at the rising edge of the CLK
Synchronous if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the 2-bit counter.
Input-
Byte Write Select Inputs, Active LOW.
Qualified with BWE to conduct byte writes to the SRAM.
BW
A
, BW
B
,
BW
C
, BW
D
Synchronous Sampled on the rising edge of CLK.
GW
CLK
CE
1
CE
2
CE
3
OE
Input-
Global Write Enable Input, Active LOW.
When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BW
X
and BWE).
Input-
Clock
Clock Input.
Captures all synchronous inputs to the device. Also used to increment the burst counter
when ADV is asserted LOW during a burst operation.
Input-
Chip Enable 1 Input, Active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
Synchronous and CE
3
to select or deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only when a
new external address is loaded.
Input-
Chip Enable 2 Input, Active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
3
to select or deselect the device. CE
2
is sampled only when a new external address is loaded.
Input-
Chip Enable 3 Input, Active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
Synchronous and CE
2
to select or deselect the device. CE
3
is sampled only when a new external address is loaded.
Input-
Output Enable, Asynchronous Input, Active LOW.
Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Input-
Advance Input Signal, Sampled on the Rising Edge of CLK.
When asserted, it automatically
Synchronous increments the address in a burst cycle.
Input-
Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW.
When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
Input-
Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW.
When asserted
Synchronous LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
Byte Write Enable Input, Active LOW.
Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
Input-
ZZ “Sleep” Input, Active HIGH.
When asserted HIGH, places the device in a non time-critical “sleep”
Asynchronous condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ
pin has an internal pull down.
I/O-
Bidirectional Data I/O Lines.
As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled
by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
s
and DQP
X
are placed
in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence,
the first clock when emerging from a deselected state, and when the device is deselected, regardless of
the state of OE.
I/O-
Bidirectional Data Parity I/O Lines.
Functionally, these signals are identical to DQ
s
. During write
Synchronous sequences, DQP
x
is controlled by BW
X
correspondingly.
Input-Static
Selects Burst Order.
When tied to GND, selects linear burst sequence. When tied to V
DD
or left floating,
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode Pin has an internal pull up.
Power Supply
Power Supply Inputs to the Core of the Device.
I/O Power
Supply
Ground
Power Supply for the I/O Circuitry.
Ground for the Core of the Device.
ADV
ADSP
ADSC
BWE
ZZ
DQ
s
DQP
X
MODE
V
DD
V
DDQ
V
SS
Document Number: 001-74847 Rev. *B
Page 5 of 21
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