CY7C1471V33
72-Mbit (2 M × 36) Flow-Through SRAM with
NoBL™ Architecture
72-Mbit (2 M × 36) Flow-Through SRAM with NoBL™ Architecture
Features
■
■
■
■
■
■
■
■
■
Functional Description
The CY7C1471V33 is 3.3 V, 2 M × 36 synchronous flow through
burst SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471V33 is equipped with the advanced
No Bus Latency (NoBL) logic required to enable consecutive
read or write operations with data being transferred on every
clock cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle.Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by two or four byte write select
(BW
X
) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
Supports up to 133 MHz bus operations with zero wait states
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte Write capability
3.3 V/2.5 V I/O supply (V
DDQ
)
Fast clock-to-output times
❐
6.5 ns (for 133-MHz device)
Clock enable (CEN) pin to enable clock and suspend operation
Synchronous self timed writes
Asynchronous output enable (OE)
CY7C1471V33 available in JEDEC-standard Pb-free 100-pin
TQFP
Three chip enables (CE
1
, CE
2
, CE
3
) for simple depth
expansion
Automatic power down feature available using ZZ mode or CE
deselect
Burst capability – linear or interleaved burst order
Low standby power
■
■
■
■
■
■
■
■
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
133 MHz
6.5
305
120
Unit
ns
mA
mA
Errata:
For information on silicon errata, see
"Errata"
on page 19. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05288 Rev. *Q
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 24, 2013
CY7C1471V33
Logic Block Diagram – CY7C1471V33
ADDRESS
REGISTER
CE
A0, A1, A
MODE
CLK
CEN
C
A1
D1
A0
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
BURST
LOGIC
Q1 A1'
A0'
Q0
ADV/LD
BW
A
BW
B
BW
C
BW
D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
DQP
C
DQP
D
OE
CE1
CE2
CE3
ZZ
INPUT
REGISTER
READ LOGIC
E
SLEEP
CONTROL
Document Number: 38-05288 Rev. *Q
Page 2 of 23
CY7C1471V33
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 18
Document Conventions ................................................. 18
Units of Measure ....................................................... 18
Errata ............................................................................... 19
Part Numbers Affected .............................................. 19
Product Status ........................................................... 19
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 38-05288 Rev. *Q
Page 3 of 23
CY7C1471V33
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
[1]
BW
D
BW
C
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
WE
OE
ADV/LD
A
82
A
100
A
99
A
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
A
BYTE C
BYTE D
DQP
C
DQ
C
DQ
C
V
DDQ
V
SS
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
V
SS
V
DDQ
DQ
D
DQ
D
DQP
D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
81
A
CY7C1471V33
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
45
46
47
48
49
50
DQP
B
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
39
40
41
42
43
A1
A0
V
SS
MODE
V
DD
A
A
A
A
44
A
A
NC/144M
A
A
Note
1. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 19.
Document Number: 38-05288 Rev. *Q
NC/288M
A
A
A
A
A
Page 4 of 23
CY7C1471V33
Pin Definitions
Name
A
0
, A
1
, A
I/O
Description
Input-
Address inputs used to select one of the address locations.
Sampled at the rising edge of the CLK.
synchronous A
[1:0]
are fed to the two-bit burst counter.
Input-
Byte write inputs, active LOW.
Qualified with WE to conduct writes to the SRAM. Sampled on the rising
BW
A
, BW
B
,
BW
C
, BW
D
synchronous edge of CLK.
WE
ADV/LD
Input-
Write enable input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
Input-
Advance/load input.
Advances the on-chip address counter or loads a new address. When HIGH (and
synchronous CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded
into the device for an access. After being deselected, ADV/LD should must driven LOW to load a new
address.
Input-
clock
Clock input.
Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CLK
CE
1
CE
2
CE
3
OE
Input-
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
synchronous and CE
3
to select or deselect the device.
Input-
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
3
to select or deselect the device.
Input-
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
2
to select or deselect the device.
Input-
Output enable, asynchronous input, active LOW.
Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are enabled to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device is deselected.
Input-
Clock enable input, active LOW.
When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the
device, use CEN to extend the previous cycle when required.
Input-
ZZ “sleep” input.
This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull-down.
I/O-
Bidirectional data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ
s
and DQP
X
are placed in a tri-state condition.The outputs are automatically tri-stated during the data portion of a
write sequence, during the first clock when emerging from a deselected state, and when the device is
deselected, regardless of the state of OE.
I/O-
Bidirectional data parity I/O lines.
Functionally, these signals are identical to DQ
s
. During write
synchronous sequences, DQP
X
is controlled by BW
X
correspondingly.
Input strap pin
Mode input.
Selects the burst order of the device. When tied to GND selects linear burst sequence.
When tied to V
DD
or left floating selects interleaved burst sequence.
Power supply
Power supply inputs to the core of the device.
I/O power
supply
Ground
–
Power supply for the I/O circuitry.
Ground for the device.
No connects.
Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion
pins and are not internally connected to the die.
CEN
ZZ
[2]
DQ
s
DQP
X
MODE
V
DD
V
DDQ
V
SS
NC
Note
2. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 19.
Document Number: 38-05288 Rev. *Q
Page 5 of 23
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
