CY7C1353G
4-Mbit (256 K × 18) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (256 K × 18) Flow-Through SRAM with NoBL™ Architecture
Features
■
Functional Description
The CY7C1353G is a 3.3 V, 256 K × 18 synchronous
flow-through burst SRAM designed specifically to support
unlimited true back-to-back read/write operations without the
insertion of wait states. The CY7C1353G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to enable
consecutive read/write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 8.0 ns (100-MHz device).
Write operations are controlled by the two byte write select
(BW
[A:B]
) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Supports up to 100-MHz bus operations with zero wait states
❐
Data is transferred on every clock
Pin compatible and functionally equivalent to ZBT™ devices
Internally self timed output buffer control to eliminate the need
to use OE
Registered inputs for flow-through operation
Byte write capability
256 K × 18 common I/O architecture
2.5 V / 3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
❐
8.0 ns (for 100-MHz device)
Clock enable (CEN) pin to suspend operation
Synchronous self timed writes
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
Burst capability – linear or interleaved burst order
Low standby power
■
■
■
■
■
■
■
■
■
■
■
■
■
Logic Block Diagram
A0, A1, A
MODE
CLK
CEN
C
CE
ADV/LD
C
WRITE ADDRESS
REGISTER
ADDRESS
REGISTER
A1
D1
A0
D0
Q1 A1'
A0'
Q0
BURST
LOGIC
ADV/LD
BW
A
BW
B
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
E
DQs
DQP
A
DQP
B
WE
OE
CE
1
CE
2
CE
3
ZZ
INPUT E
REGISTER
READ LOGIC
SLEEP
CONTROL
Errata:
For information on silicon errata, see
"Errata"
on page 16. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05515 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 24, 2013
CY7C1353G
Contents
Selection Guide ................................................................ 3
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Burst Read Accesses .................................................. 5
Single Write Accesses ................................................. 5
Burst Write Accesses .................................................. 5
Sleep Mode ................................................................. 6
Linear Burst Address Table ......................................... 6
Interleaved Burst Address Table ................................. 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Partial Truth Table for Read/Write .................................. 7
Maximum Ratings ............................................................. 8
Operating Range ............................................................... 8
Electrical Characteristics ................................................. 8
Capacitance ...................................................................... 9
Thermal Resistance .......................................................... 9
AC Test Loads and Waveforms ....................................... 9
Switching Characteristics .............................................. 10
Switching Waveforms .................................................... 11
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagram ............................................................ 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Errata ............................................................................... 16
Part Numbers Affected .............................................. 16
Product Status ........................................................... 16
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Document Number: 38-05515 Rev. *L
Page 2 of 19
CY7C1353G
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
100 MHz
8.0
205
40
Unit
ns
mA
mA
Pin Configuration
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
[1]
ADV/LD
NC/18M
BW
B
BW
A
CE
1
CE
2
CE
3
V
DD
V
SS
CEN
CLK
WE
NC
NC
OE
NC/9M
A
A
A
82
100
99
94
91
98
97
96
95
93
92
90
89
88
87
86
85
84
83
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
81
A
CY7C1353G
BYTE B
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
BYTE A
A1
A0
NC/144M
V
SS
NC/288M
MODE
V
DD
A
A
A
A
A
A
A
NC/72M
NC/36M
Note
1. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 16.
Document Number: 38-05515 Rev. *L
A
A
A
A
Page 3 of 19
CY7C1353G
Pin Definitions
Name
A
0
, A
1
, A
BW
[A:B]
WE
ADV/LD
I/O
Description
Input-
Address inputs used to select one of the 256 K address locations.
Sampled at the rising edge of
synchronous the CLK. A
[1:0]
are fed to the two-bit burst counter.
Input-
Byte write inputs, active LOW.
Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
Input-
Write enable input, active LOW.
Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
Input-
Advance/load input.
Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD must be driven LOW to load a
new address.
Input-clock
Clock input.
Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CLK
CE
1
CE
2
CE
3
OE
Input-
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
,
synchronous and CE
3
to select/deselect the device.
Input-
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
3
to select/deselect the device.
Input-
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
2
to select/deselect the device.
Input-
Output enable, asynchronous input, active LOW.
Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
Input-
Clock enable input, active LOW.
When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. While deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
Input-
ZZ “sleep” Input.
This active HIGH input places the device in a non-time critical “sleep” condition with
asynchronous data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an
internal pull-down.
I/O-
Bidirectional data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ
s
and
DQP
[A:B]
are placed in a tri-state condition. The outputs are automatically tri-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected state, and when the
device is deselected, regardless of the state of OE.
I/O-
Bidirectional data parity I/O lines.
Functionally, these signals are identical to DQ
s
. During write
synchronous sequences, DQP
[A:B]
is controlled by BW
x
correspondingly.
Input strap pin
MODE input. Selects the burst order of the device.
When tied to GND selects linear burst sequence. When tied to V
DD
or left floating selects interleaved
burst sequence.
Power supply
Power supply inputs to the core of the device.
I/O power
supply
Ground
Power supply for the I/O circuitry.
Ground for the device.
CEN
ZZ
[2]
DQ
s
DQP
[A:B]
MODE
V
DD
V
DDQ
V
SS
Note
2. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 16.
Document Number: 38-05515 Rev. *L
Page 4 of 19
CY7C1353G
Pin Definitions
(continued)
Name
NC, NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M
I/O
–
Description
No Connects.
Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M, are
address expansion pins are not internally connected to the die.
Functional Overview
The CY7C1353G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during write-read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (t
CDV
) is 8.0 ns
(100-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE
1
, CE
2
, CE
3
) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device is latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW
[A:B]
can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self timed write circuitry.
Three synchronous chip enables (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipe lined. ADV/LD
must be driven LOW after the device has been deselected to
load a new address for the next operation.
counter is determined by the MODE input signal. A LOW input
on MODE selects a linear burst mode, a HIGH selects an
interleaved burst sequence. Both burst counters use A0 and A1
in the burst sequence, and wraps around when incremented
sufficiently. A HIGH input on ADV/LD increments the internal
burst counter regardless of the state of chip enable inputs or WE.
WE is latched at the beginning of a burst cycle. Therefore, the
type of access (read or write) is maintained throughout the burst
sequence.
Single Write Accesses
Write access are initiated when these conditions are satisfied at
clock rise:
■
■
■
CEN is asserted LOW
CE
1
, CE
2
, and CE
3
are all asserted active
The write signal WE is asserted LOW.
The address presented to the address bus is loaded into the
address register. The write signals are latched into the control
logic block. The data lines are automatically tri-stated regardless
of the state of the OE input signal. This allows the external logic
to present the data on DQs and DQP
[A:B]
.
On the next clock rise the data presented to DQs and DQP
[A:B]
(or a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by
BW
[A:B]
signals. The CY7C1353G provides byte write capability
that is described in the truth table. Asserting the write enable
input (WE) with the selected byte write select input selectively
writes to only the desired bytes. Bytes not selected during a byte
write operation remains unaltered. A synchronous self timed
write mechanism has been provided to simplify the write
operations. Byte write capability has been included to greatly
simplify read/modify/write sequences, which can be reduced to
simple byte write operations.
Because the CY7C1353G is a common I/O device, data must not
be driven into the device while the outputs are active. The output
enable (OE) can be deasserted HIGH before presenting data to
the DQs and DQP
[A:B]
inputs. Doing so tri-states the output
drivers. As a safety precaution, DQs and DQP
[A:B]
.are
automatically tri-stated during the data portion of a write cycle,
regardless of the state of OE.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and 4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 8.0 ns (100-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output is tri-stated immediately.
Burst Read Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
driven LOW to load a new address into the SRAM, as described
in the
Single Read Accesses
section. The sequence of the burst
Document Number: 38-05515 Rev. *L
Burst Write Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
write operations without reasserting the address inputs. ADV/LD
Page 5 of 19
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