CY7C1347G
4-Mbit (128 K × 36) Pipelined Sync SRAM
4-Mbit (128 K × 36) Pipelined Sync SRAM
Features
■
■
■
■
■
■
■
■
■
■
■
■
Functional Description
The CY7C1347G is a 3.3 V, 128 K × 36 synchronous pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic. CY7C1347G I/O pins can operate at
either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant
when V
DDQ
= 2.5 V. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise is
2.6 ns (250 MHz device). CY7C1347G supports either the
interleaved burst sequence used by the Intel Pentium processor
or a linear burst sequence used by processors such as the
PowerPC. The burst sequence is selected through the MODE
pin. Accesses can be initiated by asserting either the address
strobe from processor (ADSP) or the address strobe from
controller (ADSC) at clock rise. Address advancement through
the burst sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the four Byte Write Select
(BW
[A:D]
) inputs. A global write enable (GW) overrides all byte
write inputs and writes data to all four bytes. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To provide proper data
during depth expansion, OE is masked during the first clock of a
read cycle when emerging from a deselected state.
Fully registered inputs and outputs for pipelined operation
128 K × 36 common I/O architecture
3.3 V core power supply (V
DD
)
2.5- / 3.3-V I/O power supply (V
DDQ
)
Fast clock to output times: 2.6 ns (for 250 MHz device)
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed writes
Asynchronous output enable
Offered in Pb-free 100-pin TQFP, Pb-free 119-ball BGA
package
“ZZ” sleep mode option and stop clock option
Available in commercial temperature range
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
250 MHz
2.6
325
40
200 MHz
2.8
265
40
166 MHz
3.5
240
40
133 MHz
4.0
225
40
Unit
ns
mA
mA
Errata:
For information on silicon errata, see
"Errata"
on page 23. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05516 Rev. *N
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 25, 2013
CY7C1347G
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
LOGIC
Q0
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document Number: 38-05516 Rev. *N
Page 2 of 26
CY7C1347G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 6
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 8
Sleep Mode ................................................................. 8
Interleaved Burst Sequence ........................................ 8
Linear Burst Sequence ................................................ 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Partial Truth Table for Read/Write ................................ 10
Maximum Ratings ........................................................... 11
Operating Range ............................................................. 11
Neutron Soft Error Immunity ......................................... 11
Electrical Characteristics ............................................... 11
Capacitance .................................................................... 12
Thermal Resistance ........................................................ 12
AC Test Loads and Waveforms ..................................... 13
Switching Characteristics .............................................. 14
Switching Waveforms .................................................... 15
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 22
Document Conventions ................................................. 22
Units of Measure ....................................................... 22
Errata ............................................................................... 23
Part Numbers Affected .............................................. 23
Product Status ........................................................... 23
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC® Solutions ...................................................... 26
Cypress Developer Community ................................. 26
Technical Support ..................................................... 26
Document Number: 38-05516 Rev. *N
Page 3 of 26
CY7C1347G
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
[1]
BYTE C
BYTE D
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1347G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
Note
1. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 23.
Document Number: 38-05516 Rev. *N
MODE
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
NC/18M
NC/9M
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 4 of 26
CY7C1347G
Pin Configurations
(continued)
Figure 2. 119-ball BGA (14 × 22 × 2.4 mm) pinout
[2]
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288 M
NC/144 M
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
A
CE
2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
A
NC/72M
NC
3
A
A
A
V
SS
V
SS
V
SS
BW
C
V
SS
NC
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
NC
5
A
A
A
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
A
NC
6
A
CE
3
A
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC/36M
NC
7
V
DDQ
NC/576 M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
Note
2. Errata:
The ZZ ball (T7) needs to be externally connected to ground. For more information, see
"Errata"
on page 23.
Document Number: 38-05516 Rev. *N
Page 5 of 26
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
