CY7C1345G
4-Mbit (128 K × 36) Flow-Through Sync SRAM
4-Mbit (128 K × 36) Flow through Sync SRAM
Features
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Functional Description
The CY7C1345G is a 128 K × 36 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. The maximum access delay from clock rise
is 8.0 ns (100 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive edge triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address pipelining chip enable (CE
1
), depth expansion
chip enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
x
, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1345G enables either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses are initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) is active. Subsequent burst addresses
are internally generated as controlled by the Advance pin (ADV).
The CY7C1345G operates from a +3.3 V core power supply
while all outputs operate with either a +2.5 or +3.3 V supply. All
inputs and outputs are JEDEC standard JESD8-5 compatible.
128 K × 36 common I/O
3.3 V core power supply (V
DD
)
2.5 V or 3.3 V I/O supply (V
DDQ
)
Fast clock-to-output times
❐
8.0 ns (100 MHz version)
Provide high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
ZZ sleep mode option
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Selection Guide
Description
Maximum access time
Maximum operating current
Maximum standby current
100 MHz
8.0
205
40
Unit
ns
mA
mA
Errata:
For information on silicon errata, see
"Errata"
on page 21. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05517 Rev. *L
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 25, 2013
CY7C1345G
Logic Block Diagram
A 0, A1, A
ADDRESS
REGISTER
A
[1:0]
MODE
ADV
CLK
BURST Q1
COUNTER
AND LOGIC
Q0
CLR
ADSC
ADSP
DQ
D
,
DQP
D
BW
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BYTE
WRITE REGISTER
DQ
A
,
DQP
A
BW
A
BWE
GW
CE1
CE2
CE3
OE
DQ
A
,
DQP
A
BYTE
WRITE REGISTER
BYTE
WRITE REGISTER
DQ
D
,
DQP
D
BYTE
WRITE REGISTER
DQ
C
,
DQP
C
BYTE
WRITE REGISTER
DQ
B
,
DQP
B
BW
B
BYTE
WRITE REGISTER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQ s
DQP
A
DQP
B
DQP
C
DQP
D
ENABLE
REGISTER
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document Number: 38-05517 Rev. *L
Page 2 of 24
CY7C1345G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 7
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read or Write .......................................... 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Neutron Soft Error Immunity ......................................... 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
AC Test Loads and Waveforms ..................................... 12
Switching Characteristics .............................................. 13
Timing Diagrams ............................................................ 14
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Errata ............................................................................... 21
Part Numbers Affected .............................................. 21
Product Status ........................................................... 21
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC® Solutions ...................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Document Number: 38-05517 Rev. *L
Page 3 of 24
CY7C1345G
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
[1]
BW
D
BW
C
BW
B
BW
A
CE
3
CE
1
V
DD
V
SS
OE
ADSC
ADSP
ADV
86
85
84
83
CE
2
CLK
GW
BWE
A
A
82
A
99
98
97
96
95
94
93
92
91
90
89
88
87
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
BYTE C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
100
81
A
CY7C1345G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44
45
46
47
48
49
50
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
38
39
40
41
V
DD
42
NC/18M
NC/72M
NC/36M
MODE
A
NC/9M
A
A
A
1
A
0
V
SS
A
A
A
43
A
A
A
A
Note
1. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 21.
Document Number: 38-05517 Rev. *L
A
Page 4 of 24
CY7C1345G
Pin Definitions
Name
A
0
, A
1
, A
I/O
Description
Input
Address inputs used to select one of the 128 K address locations.
Sampled at the rising edge of
synchronous the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the two
bit counter.
BW
A,
BW
B
,
Input
Byte write select inputs, active LOW.
Qualified with BWE to conduct byte writes to the SRAM. Sampled
BW
C
, BW
D
synchronous on the rising edge of CLK.
GW
BWE
CLK
CE
1
Input
Global write enable input, active LOW.
When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (all bytes are written, regardless of the values on BW
[A:D]
and BWE).
Input
Byte write enable input, active LOW.
Sampled on the rising edge of CLK. This signal is asserted LOW
synchronous to conduct a byte write.
Input clock
Clock input.
Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Input
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
synchronous and CE
3
to select or deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only when a
new external address is loaded.
Input
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
3
to select or deselect the device. CE
2
is sampled only when a new external address is loaded.
Input
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
2
to select or deselect the device. CE
3
is sampled only when a new external address is loaded.
Input
Output enable, asynchronous input, active LOW.
Controls the direction of the IO pins. When LOW,
asynchronous the IO pins act as outputs. When deasserted HIGH, IO pins are tristated and act as input data pins. OE
is masked during the first clock of a read cycle when emerging from a deselected state.
Input
Advance input signal,
Sampled on the Rising Edge of CLK. When asserted, it automatically increments
synchronous the address in a burst cycle.
Input
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
Input
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input
ZZ sleep input, active HIGH.
When asserted HIGH places the device in a non-time critical sleep
asynchronous condition with data integrity preserved. During normal operation, this pin is low or left floating. ZZ pin has
an internal pull-down.
IO
Bidirectional data IO lines.
As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins act as outputs. When HIGH, DQs and DQP
[A:D]
are placed in a tristate condition.
Power supply
Power supply inputs to the core of the device.
Ground
IO power
supply
IO ground
Ground for the core of the device.
Power supply for the IO circuitry.
Ground for the IO circuitry.
CE
2
CE
3
OE
ADV
ADSP
ADSC
ZZ
[2]
DQs,
DQP
A
,
DQP
B
,
DQP
C
,
DQP
D
V
DD
V
SS
V
DDQ
V
SSQ
Note
2. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 21.
Document Number: 38-05517 Rev. *L
Page 5 of 24
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