CY7C1325G
4-Mbit (256 K × 18) Flow-Through
Sync SRAM
4-Mbit (256 K × 18) Flow-Through Sync SRAM
Features
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Functional Description
The CY7C1325G is a 256 K × 18 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
6.5 ns (133 MHz version). A 2 bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE
1
), depth-expansion
chip enables (CE
2
and CE
3
), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW
[A:B]
, and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
The CY7C1325G allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1325G operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
256 K × 18 common I/O
3.3 V core power supply (V
DD
)
2.5 V or 3.3 V I/O power supply (V
DDQ
)
Fast clock-to-output times
6.5 ns (133 MHz version)
Provide high performance 2-1-1-1 access rate
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self timed write
Asynchronous output enable
Available in Pb-free 100-pin TQFP package
“ZZ” sleep mode option
Logic Block Diagram
A 0,A1,A
MODE
ADDRESS
REGISTER
A[1:0]
ADV
CLK
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADSC
ADSP
DQ
B
,DQP
B
WRITE REGISTER
DQ
B
,DQP
B
WRITE DRIVER
BW
B
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
BW
A
BWE
GW
DQ
A
,DQP
A
WRITE REGISTER
DQ
A
,DQP
A
WRITE DRIVER
INPUT
REGISTERS
DQs
DQP
A
DQP
B
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
ZZ
SLEEP
CONTROL
Errata:
For information on silicon errata, see
"Errata"
on page 20. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05518 Rev. *M
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 26, 2013
CY7C1325G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Single Write Accesses Initiated by ADSP ................... 5
Single Write Accesses Initiated by ADSC ................... 5
Burst Sequences ......................................................... 5
Sleep Mode ................................................................. 5
Interleaved Burst Address Table ................................. 6
Linear Burst Address Table ......................................... 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Truth Table for Read/Write .............................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Neutron Soft Error Immunity ........................................... 9
Electrical Characteristics ................................................. 9
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Errata ............................................................................... 20
Part Numbers Affected .............................................. 20
Product Status ........................................................... 20
Ram9 Sync/NoBL ZZ Pin Issues Errata Summary .... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 23
Worldwide Sales and Design Support ....................... 23
Products .................................................................... 23
PSoC® Solutions ...................................................... 23
Cypress Developer Community ................................. 23
Technical Support ..................................................... 23
Document Number: 38-05518 Rev. *M
Page 2 of 23
CY7C1325G
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum standby current
133 MHz
6.5
225
40
Unit
ns
mA
mA
Pin Configurations
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
[1]
BW
B
BW
A
CE
3
CE
1
CE
2
NC
NC
V
DD
V
SS
CLK
OE
ADSC
ADSP
ADV
A
86
85
84
83
82
GW
BWE
A
A
99
98
97
96
95
94
93
92
91
90
89
88
87
NC
NC
NC
V
DDQ
V
SS
NC
NC
DQ
B
DQ
B
V
SS
V
DDQ
DQ
B
DQ
B
NC
V
DD
NC
V
SS
DQ
B
DQ
B
V
DDQ
V
SS
DQ
B
DQ
B
DQP
B
NC
V
SS
V
DDQ
NC
NC
NC
BYTE B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
100
81
A
CY7C1325G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
44
45
46
47
48
49
50
A
NC
NC
V
DDQ
V
SS
NC
DQP
A
DQ
A
DQ
A
V
SS
V
DDQ
DQ
A
DQ
A
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SS
DQ
A
DQ
A
NC
NC
V
SS
V
DDQ
NC
NC
NC
BYTE A
38
39
40
41
42
NC/72M
NC/36M
V
DD
NC/18M
MODE
A
NC/9M
A
A
A
1
A
0
V
SS
A
A
A
43
A
A
A
A
Note
1. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 20.
Document Number: 38-05518 Rev. *M
A
Page 3 of 23
CY7C1325G
Pin Definitions
Name
A
0
, A
1
, A
I/O
Description
Input-
Address inputs used to select one of the 256 K address locations.
Sampled at the rising edge of
synchronous the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feed the 2
bit counter.
Input-
Byte write select inputs, active LOW.
Qualified with BWE to conduct byte writes to the SRAM. Sampled
synchronous on the rising edge of CLK.
Input-
Global write enable input, active LOW.
When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (all bytes are written, regardless of the values on BW
[A:B]
and BWE).
Input-
Byte write enable input, active LOW.
Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
Input-clock
Clock input.
Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
BW
A,
BW
B
GW
BWE
CLK
CE
1
Input-
Chip enable 1 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
synchronous and CE
3
to select/deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only when a
new external address is loaded.
Input-
Chip enable 2 input, active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
3
to select/deselect the device. CE
2
is sampled only when a new external address is loaded.
Input-
Chip enable 3 input, active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
synchronous and CE
2
to select/deselect the device. CE
3
is sampled only when a new external address is loaded.
Input-
Output enable, asynchronous input, active LOW.
Controls the direction of the I/O pins. When LOW,
asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Input-
Advance input signal, sampled on the rising edge of CLK.
When asserted, it automatically
synchronous increments the address in a burst cycle.
Input-
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE
1
is deasserted HIGH.
Input-
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Input-
ZZ “sleep” input, active HIGH.
When asserted HIGH places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ
pin has an internal pull-down.
I/O-
Bidirectional data I/O lines.
As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP
[A:B]
are placed in a tristate condition.
Power supply
Power supply inputs to the core of the device.
Ground
I/O power
supply
Input-
static
–
Ground for the core of the device.
Power supply for the I/O circuitry.
Selects burst order.
When tied to GND selects linear burst sequence. When tied to V
DD
or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
No connects.
Not Internally connected to the die.
CE
2
CE
3
OE
ADV
ADSP
ADSC
ZZ
[2]
DQs
DQP
A,
DQP
B
V
DD
V
SS
V
DDQ
MODE
NC
Note
2. Errata:
The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see
"Errata"
on page 20.
Document Number: 38-05518 Rev. *M
Page 4 of 23
CY7C1325G
Pin Definitions
(continued)
Name
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
I/O
–
Description
No connects.
Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t
CDV
) is 6.5 ns (133 MHz device).
The CY7C1325G supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW
[A:B]
) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous chip selects (CE
1
, CE
2
, CE
3
) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE
1
is
HIGH.
appropriate states that indicate a write) on the next clock rise, the
appropriate data is latched and written into the device. Byte
writes are allowed. During byte writes, BW
A
controls DQ
A
and
BW
B
controls DQ
B
. All I/Os are tristated during a byte write.Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tristated prior to the
presentation of data to DQ
s
. As a safety precaution, the data
lines are tristated after a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW
[A:B]
)
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ
[A:D]
is written into the
specified address location. Byte writes are allowed. During byte
writes, BW
A
controls DQ
A
, BW
B
controls DQ
B
. All I/Os are
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the presen-
tation of data to DQ
s
. As a safety precaution, the data lines are
tristated after a write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1325G provides an on-chip two bit wraparound burst
counter inside the SRAM. The burst counter is fed by A
[1:0]
, and
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to a interleaved burst sequence.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE
1
, CE
2
, and CE
3
are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs, a maximum to t
CDV
after clock rise. ADSP is ignored if
CE
1
is HIGH.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of t
ZZREC
after the ZZ input returns LOW.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE
1
, CE
2
, CE
3
are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BW
[A:B]
) are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
Document Number: 38-05518 Rev. *M
Page 5 of 23
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