CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
64-Kbit (8 K × 8) SPI nvSRAM
64-Kbit (8 K × 8) SPI nvSRAM
Features
■
■
64-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 8 K × 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE)
❐
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐
Support automatic STORE on power-down with a small
capacitor (except for CY14MX064Q1B)
High reliability
❐
Industry standard configurations
❐
Operating voltages:
• CY14MB064Q1B/CY14MB064Q2B: V
CC
= 2.7 V to 3.6 V
• CY14ME064Q1B/CY14ME064Q2B: V
CC
= 4.5 V to 5.5 V
❐
Industrial temperature
❐
8-pin small outline integrated circuit (SOIC) package
❐
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14MX064Q combines a 64 Kbit nvSRAM with a
nonvolatile element in each memory cell with serial SPI interface.
The memory is organized as 8 K words of 8 bits each. The
embedded nonvolatile elements incorporate the QuantumTrap
technology, creating the world’s most reliable nonvolatile
memory. The SRAM provides infinite read and write cycles, while
the QuantumTrap cells provide highly reliable nonvolatile
storage of data. Data transfers from SRAM to the nonvolatile
elements (STORE operation) takes place automatically at
power-down (except for CY14MX064Q1B). On power-up, data
is restored to the SRAM from the nonvolatile memory (RECALL
operation). You can also initiate the STORE and RECALL
operations through SPI instruction.
■
Infinite read, write, and RECALL cycles
❐
1million STORE cycles to QuantumTrap
❐
Data retention: 20 years at 85
C
■
High speed serial peripheral interface (SPI)
❐
40-MHz clock rate SPI write and read with zero cycle delay
❐
Supports SPI mode 0 (0,0) and mode 3 (1,1)
■
SPI access to special functions
❐
Nonvolatile STORE/RECALL
❐
8-byte serial number
❐
Manufacturer ID and Product ID
❐
Sleep mode
Write protection
❐
Hardware protection using Write Protect (WP) pin
❐
Software protection using Write Disable instruction
❐
Software block protection for 1/4, 1/2, or entire array
Low power consumption
❐
Average active current of 3 mA at 40 MHz operation
❐
Average standby mode current of 120
A
❐
Sleep mode current of 8
A
Configuration
Feature
AutoStore
Software STORE
CY14MX064Q1B
No
Yes
CY14MX064Q2B
Yes
Yes
■
■
Logic Block Diagram
Serial Number
8x8
Manufacturer ID /
Product ID
Status Register
WRSR/RDSR/WREN
SI
CS
SCK
WP
SO
V
CC
V
CAP
SPI Control Logic
Write Protection
Instruction decoder
QuantumTrap
8Kx8
SRAM
8Kx8
STORE
RECALL
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data & Address
Control
Power Control Block
SLEEP
Cypress Semiconductor Corporation
Document Number: 001-70382 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 6, 2013
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Contents
Pinout ................................................................................ 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Write ................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation .................................................... 4
Software STORE Operation ........................................ 5
RECALL Operation ...................................................... 5
Hardware RECALL (Power-Up) .................................. 5
Software RECALL ....................................................... 5
Disabling and Enabling AutoStore ............................... 5
Serial Peripheral Interface ............................................... 6
SPI Overview ............................................................... 6
SPI Modes ................................................................... 7
SPI Operating Features .................................................... 8
Power-Up .................................................................... 8
Power-Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection ......................... 11
Write Enable (WREN) Instruction .............................. 11
Write Disable (WRDI) Instruction .............................. 11
Block Protection ........................................................ 12
Hardware Write Protection (WP) ............................... 12
Memory Access .............................................................. 12
Read Sequence (READ) Instruction .......................... 12
Write Sequence (WRITE) Instruction ........................ 12
nvSRAM Special Instructions ........................................ 14
Software STORE (STORE) Instruction ..................... 14
Software RECALL (RECALL) Instruction .................. 14
AutoStore Enable (ASENB) Instruction ..................... 14
AutoStore Disable (ASDISB) Instruction ................... 15
Special Instructions ....................................................... 15
SLEEP Instruction ..................................................... 15
Serial Number ................................................................. 15
WRSN (Serial Number Write) Instruction .................. 15
RDSN (Serial Number Read) Instruction ................... 16
Device ID ......................................................................... 16
RDID (Device ID Read) Instruction ........................... 17
HOLD Pin Operation ................................................. 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
DC Electrical Characteristics ........................................ 18
Data Retention and Endurance ..................................... 19
Capacitance .................................................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 20
AC Test Conditions ........................................................ 20
AC Switching Characteristics ....................................... 21
Switching Waveforms .................................................... 21
AutoStore or Power-Up RECALL .................................. 22
Software Controlled STORE and RECALL Cycles ...... 23
Switching Waveforms .................................................... 23
Ordering Information ...................................................... 24
Ordering Code Definitions ......................................... 24
Package Diagrams .......................................................... 25
Acronyms ........................................................................ 26
Document Conventions ................................................. 26
Units of Measure ....................................................... 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC Solutions ......................................................... 28
Document Number: 001-70382 Rev. *H
Page 2 of 28
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Pinout
Figure 1. 8-pin SOIC pinout
[1, 2]
CS
1
2
3
4
8
CY14MX064Q1B
7
Top View
6
not to scale
5
VCC
HOLD
SCK
SI
CS
1
2
3
4
8
CY14MX064Q2B
7
Top View
6
not to scale
5
VCC
HOLD
SCK
SI
SO
WP
VSS
SO
V
CAP
VSS
Pin Definitions
Pin Name
[1, 2]
CS
SCK
SI
SO
WP
HOLD
V
CAP
I/O Type
Input
Input
Input
Output
Input
Input
Description
Chip Select.
Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
Serial Clock.
Runs at speeds up to a maximum of f
SCK
. Serial input is latched at the rising edge of
this clock. Serial output is driven at the falling edge of the clock.
Serial Input.
Pin for input of all SPI instructions and data.
Serial Output.
Pin for output of data through SPI.
Write Protect.
Implements hardware write protection in SPI.
HOLD Pin.
Suspends serial operation.
Power supply
AutoStore Capacitor.
Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
No connect
No Connect:
This pin is not connected to the die.
Power supply
Ground
Power supply
Power supply
NC
V
SS
V
CC
Notes
1. CY14MX064Q1B part does not have V
CAP
pin and does not support AutoStore.
2. CY14MX064Q2B part does not have WP pin.
Document Number: 001-70382 Rev. *H
Page 3 of 28
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
Device Operation
CY14MX064Q is a 64 Kbit serial (SPI) nvSRAM memory with a
nonvolatile element in each memory cell. All the reads and writes
to nvSRAM happen to the SRAM, which gives nvSRAM the
unique capability to handle infinite writes to the memory. The
data in SRAM is secured by a STORE sequence which transfers
the data in parallel to the nonvolatile QuantumTrap cells. A small
capacitor (V
CAP
) is used to AutoStore the SRAM data in
nonvolatile cells when power goes down providing power-down
data security. The QuantumTrap nonvolatile elements built in the
reliable SONOS technology make nvSRAM the ideal choice for
secure data storage.
The 64-Kbit memory array is organized as 8 K words × 8 bits.
The memory can be accessed through a standard SPI interface
that enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the Chip Select (CS) pin and
accessed through Serial Input (SI), Serial Output (SO), and
Serial Clock (SCK) pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (1/4, 1/2, or full
array) using BP0 and BP1 pins in the Status Register. Further,
the HOLD pin is used to suspend any serial communication
without resetting the serial sequence.
CY14MX064Q uses the standard SPI opcodes for memory
access. In addition to the general SPI instructions for read and
write, it provides four special instructions that allow access to
four nvSRAM specific functions: STORE, RECALL, AutoStore
Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable you to choose a part which fits in best in their application.
The feature summary is given in
Table 1.
Table 1. Feature Summary
Feature
WP
V
CAP
AutoStore
Power-Up RECALL
Software STORE
CY14MX064Q1B
Yes
No
No
Yes
Yes
CY14MX064Q2B
No
Yes
Yes
Yes
Yes
performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
SRAM Read
A read cycle is performed at the SPI bus speed. The data is read
out with zero cycle delay after the READ instruction is executed.
The READ instruction is issued through the SI pin of the nvSRAM
and consists of the READ opcode and two bytes of address. The
data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined explicitly in the Memory
Access section of SPI Protocol Description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device STOREs data to the
nonvolatile cells using one of the two STORE operations:
AutoStore, activated on device power-down; and Software
STORE, activated by a STORE instruction. During the STORE
cycle, an erase of the previous nonvolatile data is first performed,
followed by a program of the nonvolatile elements. After a
STORE cycle is initiated, read/write to CY14MX064Q is inhibited
until the cycle is completed.
The RDY bit in the Status Register can be monitored by the
system to detect if a STORE or Software RECALL cycle is in
progress. The busy status of nvSRAM is indicated RDY bit being
set to ‘1’. To avoid unnecessary nonvolatile STOREs, AutoStore
operation is ignored unless at least one write operation has taken
place since the most recent STORE or RECALL cycle. However,
software initiated STORE cycles are performed regardless of
whether a write operation has taken place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (V
CAP
) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V
CC
to
charge the capacitor connected to the V
CAP
pin. When the
voltage on the V
CC
pin drops below V
SWITCH
during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
allows you to perform infinite write operations. A write cycle is
Document Number: 001-70382 Rev. *H
Page 4 of 28
CY14MB064Q1B/CY14MB064Q2B
CY14ME064Q1B/CY14ME064Q2B
charge from the V
CAP
capacitor. The AutoStore operation is not
initiated if no write cycle has been performed since last RECALL.
Note
If a capacitor is not connected to V
CAP
pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
(AutoStore
Disable (ASDISB) Instruction on page 15).
If
AutoStore is enabled without a capacitor on the V
CAP
pin, the
device attempts an AutoStore operation without sufficient charge
to complete the STORE. This will corrupt the data stored in
nvSRAM, Status Register as well as the serial number and it will
unlock the SNL bit. To resume normal functionality, the WRSR
instruction must be issued to update the nonvolatile bits BP0,
BP1, and WPEN in the Status Register.
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for AutoStore operation. Refer to
DC Electrical
Characteristics on page 18
for the size of the V
CAP
.
Note
CY14MX064Q1B does not support AutoStore operation.
You must perform Software STORE operation by using the SPI
STORE instruction to secure the data.
Figure 2. AutoStore Mode
V
CC
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. A RECALL may be
initiated in two ways: Hardware RECALL, initiated on power-up
and Software RECALL, initiated by a SPI RECALL instruction.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
Hardware RECALL (Power-Up)
During power-up, when V
CC
crosses V
SWITCH
, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM. The data would previously
have been stored on the nonvolatile memory through a STORE
sequence.
A Power-Up RECALL cycle takes t
FA
time to complete and the
memory access is disabled during this time.
Software RECALL
0.1 uF
10 kOhm
V
CC
Software RECALL allows you to initiate a RECALL operation to
restore the content of nonvolatile memory on to the SRAM. A
Software RECALL is issued by using the SPI instruction for
RECALL.
A Software RECALL takes t
RECALL
time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
CS
V
CAP
V
CAP
V
SS
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note
CY14MX064Q2B comes with the factory with autoStore
enabled and CY14MX064Q1B/CY14MX064Q2B with 0x00
written in all cells. In CY14MX064Q1B, V
CAP
pin is not present
and AutoStore option is not available.
Note
If AutoStore is disabled and V
CAP
is not required, then the
V
CAP
pin must be left open. The V
CAP
pin must never be
connected to ground. The Power-Up RECALL operation cannot
be disabled in any case.
Software STORE Operation
Software STORE enables the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes t
STORE
time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register may be polled to find the Ready or Busy
status of the nvSRAM. After the t
STORE
cycle time is completed,
the SRAM is activated again for read and write operations.
Document Number: 001-70382 Rev. *H
Page 5 of 28
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