CY14B512Q1
CY14B512Q2
CY14B512Q3
512-Kbit (64 K × 8) Serial (SPI) nvSRAM
512-Kbit (64 K × 8) Serial (SPI) nvSRAM
Features
■
■
■
High reliability
❐
Infinite read, write, and RECALL cycles
❐
1 million STORE cycles to QuantumTrap
❐
Data retention: 20 years
High speed serial peripheral interface (SPI)
❐
40 MHz clock rate
❐
Supports SPI mode 0 (0,0) and mode 3 (1,1)
Write protection
❐
Hardware protection using Write Protect (WP) pin
❐
Software protection using Write Disable instruction
❐
Software block protection for 1/4,1/2, or entire array
Low power consumption
❐
Single 3 V +20%, –10% operation
❐
Average active current of 10 mA at 40 MHz operation
■
■
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14B512Q1
No
Yes
No
CY14B512Q2
Yes
Yes
No
CY14B512Q3
Yes
Yes
Yes
■
Logic Block Diagram
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
64 K X 8
V
CC
V
CAP
Power Control
SRAM Array
64 K X 8
STORE
RECALL
STORE/RECALL
Control
HSB
Instruction
register
D0-D7
Address
Decoder
A0-A15
SI
Data I/O register
SO
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation
Document Number: 001-53873 Rev. *I
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 24, 2013
Not Recommended for New Designs
512-Kbit nonvolatile static random access memory (nvSRAM)
❐
Internally organized as 64 K × 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (hardware STORE) or SPI instruction (Software
STORE)
❐
RECALL to SRAM initiated on power-up (power-Up
RECALL) or by SPI instruction (software RECALL)
❐
Automatic STORE on power-down with a small capacitor
(except for CY14B512Q1)
Industry standard configurations
❐
Industrial temperature
❐
CY14B512Q1 has identical pin configuration to industry
standard 8-pin NV memory
❐
8-pin dual flat no-lead (DFN) package and 16-pin small
outline integrated circuit (SOIC) package
❐
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The
Cypress
CY14B512Q1/CY14B512Q2/CY14B512Q3
combines a 512-Kbit nvSRAM
[1]
with a nonvolatile element in
each memory cell with serial SPI interface. The memory is
organized as 64 K words of 8 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
creating the world’s most reliable nonvolatile memory. The
SRAM provides infinite read and write cycles, while the
QuantumTrap cell provides highly reliable nonvolatile storage of
data. Data transfers from SRAM to the nonvolatile elements
(STORE operation) takes place automatically at power-down
(except for CY14B512Q1). On power-up, data is restored to the
SRAM from the nonvolatile memory (RECALL operation). The
STORE and RECALL operations can also be initiated by the user
through SPI instruction.
CY14B512Q1
CY14B512Q2
CY14B512Q3
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 4
Device Operation .............................................................. 5
SRAM Write ................................................................. 5
SRAM Read ................................................................ 5
STORE Operation ....................................................... 5
AutoStore Operation .................................................... 6
Software STORE Operation ........................................ 6
Hardware STORE and HSB pin Operation ................. 6
RECALL Operation ...................................................... 6
Hardware RECALL (Power-Up) .................................. 6
Software RECALL ....................................................... 7
Disabling and Enabling AutoStore ............................... 7
Serial Peripheral Interface ............................................... 7
SPI Overview ............................................................... 7
SPI Modes ................................................................... 8
SPI Operating Features .................................................... 9
Power-Up .................................................................... 9
Power On Reset .......................................................... 9
Power-Down ................................................................ 9
Active Power and Standby Power Modes ................... 9
SPI Functional Description .............................................. 9
Status Register ............................................................... 10
Read Status Register (RDSR) Instruction ................. 10
Write Status Register (WRSR) Instruction ................ 10
Write Protection and Block Protection ......................... 11
Write Enable (WREN) Instruction .............................. 11
Write Disable (WRDI) Instruction .............................. 11
Block Protection ........................................................ 11
Write Protect (WP) Pin .............................................. 12
Memory Access .............................................................. 12
Read Sequence (READ) instruction .......................... 12
Write Sequence (WRITE) instruction ........................ 12
Software STORE (STORE) instruction ...................... 14
Software RECALL (RECALL) instruction .................. 14
AutoStore Enable (ASENB) Instruction ..................... 14
AutoStore Disable (ASDISB) Instruction ................... 14
HOLD Pin Operation ................................................. 15
Maximum Ratings ........................................................... 16
Operating Range ............................................................. 16
DC Electrical Characteristics ........................................ 16
Data Retention and Endurance ..................................... 17
Capacitance .................................................................... 17
Thermal Resistance ........................................................ 17
AC Test Loads and Waveforms ..................................... 17
AC Test Conditions ........................................................ 17
AC Switching Characteristics ....................................... 18
Switching Waveforms .................................................... 18
AutoStore or Power-Up RECALL .................................. 19
Software Controlled STORE and RECALL Cycles ...... 20
Switching Waveforms .................................................... 20
Hardware STORE Cycle ................................................. 21
Switching Waveforms .................................................... 21
Ordering Information ...................................................... 22
Ordering Code Definitions ......................................... 22
Package Diagrams .......................................................... 23
Acronyms ........................................................................ 25
Document Conventions ................................................. 25
Units of Measure ....................................................... 25
Document History Page ................................................. 26
Sales, Solutions, and Legal Information ...................... 27
Worldwide Sales and Design Support ....................... 27
Products .................................................................... 27
PSoC Solutions ......................................................... 27
Document Number: 001-53873 Rev. *I
Page 2 of 27
Not Recommended for New Designs
CY14B512Q1
CY14B512Q2
CY14B512Q3
Pinouts
Figure 1. 8-pin DFN pinout
[2, 3, 4]
CY14B512Q1
CS
SO
WP
VSS
O
CY14B512Q2
8
7
VCC
HOLD
SCK
SI
CS
O
1
2
3
4
Top View
(not to scale)
EXPOSED
PAD
1
2
3
4
Top View
(not to scale)
EXPOSED
PAD
8
7
6
5
VCC
HOLD
SCK
SI
SO
VCAP
VSS
6
5
Figure 2. 16-pin SOIC pinout
NC
1
2
3
4
5
6
7
8
CY14B512Q3
Top View
not to scale
12
11
10
9
16
15
14
13
V
CC
NC
V
CAP
SO
SI
SCK
CS
HSB
NC
NC
NC
WP
HOLD
NC
V
SS
Notes
2. HSB pin is not available in 8-pin DFN packages.
3. CY14B512Q1 part does not have V
CAP
pin and does not support AutoStore.
4. CY14B512Q2 part does not have WP pin.
Document Number: 001-53873 Rev. *I
Page 3 of 27
Not Recommended for New Designs
CY14B512Q1
CY14B512Q2
CY14B512Q3
Pin Definitions
Pin Name
CS
SCK
SI
SO
WP
HOLD
HSB
I/O Type
Input
Input
Input
Output
Input
Input
Description
Chip select. Activates the device when pulled LOW. Driving this pin HIGH puts the device in low power
standby mode.
Serial clock. Runs at speeds up to maximum of f
SCK
. Serial input is latched at the rising edge of this
clock. Serial output is driven at the falling edge of the clock.
Serial input. Pin for input of all SPI instructions and data.
Serial output. Pin for output of data through SPI.
Write protect. Implements hardware write protection in SPI.
HOLD pin. Suspends serial operation.
Input/output Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB is driven HIGH for a short time (t
HHHD
) with standard output high current and then a weak
internal pull-up resistor keeps this pin HIGH (External pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It must never
be connected to ground.
No connect
No connect: This pin is not connected to the die.
Power supply Ground.
Power supply Power supply (2.7 V to 3.6 V).
No connect
The EXPOSED PAD on the bottom of 8-pin DFN package is not connected to the die. It is recommended
to connect the EXPOSED PAD to ground. Thermal vias can be used to increase thermal conductivity.
V
CAP
NC
V
SS
V
CC
EXPOSED
PAD
Document Number: 001-53873 Rev. *I
Page 4 of 27
Not Recommended for New Designs
CY14B512Q1
CY14B512Q2
CY14B512Q3
Device Operation
CY14B512Q1/CY14B512Q2/CY14B512Q3 is a 512-Kbit
nvSRAM memory with a nonvolatile element in each memory
cell. All the reads and writes to nvSRAM happen to the SRAM
which gives nvSRAM the unique capability to handle infinite
writes to the memory. The data in SRAM is secured by a STORE
sequence that transfers the data in parallel to the nonvolatile
QuantumTrap cells. A small capacitor (V
CAP
) is used to
AutoStore the SRAM data in nonvolatile cells when power goes
down providing power-down data security. The QuantumTrap
nonvolatile elements built in the reliable SONOS technology
make nvSRAM the ideal choice for secure data storage.
The 512-Kbit memory array is organized as 64 K words × 8 bits.
The memory is accessed through a standard SPI interface that
enables very high clock speeds up to 40 MHz with zero cycle
delay read and write cycles. This device supports SPI modes 0
and 3 (CPOL, CPHA = 0, 0 and 1, 1) and operates as SPI slave.
The device is enabled using the chip select (CS) pin and
accessed through serial input (SI), serial output (SO), and serial
clock (SCK) pins.
This device provides the feature for hardware and software write
protection through the WP pin and WRDI instruction respectively
along with mechanisms for block write protection (one quarter,
one half, or full array) using BP0 and BP1 pins in the Status
Register. Further, the HOLD pin can be used to suspend any
serial communication without resetting the serial sequence.
CY14B512Q1/CY14B512Q2/CY14B512Q3 uses the standard
SPI opcodes for memory access. In addition to the general SPI
instructions for read and write, it provides four special
instructions which enable access to four nvSRAM specific
functions: STORE, RECALL, AutoStore Disable (ASDISB), and
AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
The device is available in three different pin configurations that
enable the user to choose a part which fits in best in their
application
.
The feature summary is given in
Table 1.
Table 1. Feature Summary
CY14B512Q1 CY14B512Q2 CY14B512Q3
WP
Yes
No
Yes
V
CAP
No
Yes
Yes
HSB
No
No
Yes
AutoStore
No
Yes
Yes
Power-Up RECALL
Yes
Yes
Yes
Hardware STORE
No
No
Yes
Software STORE
Yes
Yes
Yes
Software RECALL
Yes
Yes
Yes
Feature
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables the user to perform infinite write operations. A write cycle
is performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
The device allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the memory access
section of SPI protocol description.
SRAM Read
A read cycle is performed at the SPI bus speed and the data is
read out with zero cycle delay after the READ instruction is
executed. The READ instruction is issued through the SI pin of
the nvSRAM and consists of the READ opcode and two bytes of
address. The data is read out on the SO pin.
This device allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the memory access
section of SPI protocol description.
STORE Operation
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The device STOREs data to the
nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated,
read/write
to
CY14B512Q1/CY14B512Q2/CY14B512Q3 is inhibited until the
cycle is completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
Document Number: 001-53873 Rev. *I
Page 5 of 27
Not Recommended for New Designs
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