CY14B256P
256-Kbit (32 K × 8) Serial (SPI) nvSRAM
with Real Time Clock
256-Kbit (32 K × 8) Serial (SPI) nvSRAM with Real Time Clock
Features
■
■
■
High reliability
❐
❐
❐
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Overview
The Cypress CY14B256P combines a 256-Kbit nvSRAM
[1]
with
a full-featured real time clock in a monolithic integrated circuit
with serial SPI interface. The memory is organized as 32 K words
of 8 bits each. The embedded nonvolatile elements incorporate
the QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM from the nonvolatile memory (RECALL operation).
The STORE and RECALL operations can also be initiated by the
user through SPI instruction.
■
Real time clock (RTC)
❐
Full-featured RTC
❐
Watchdog timer
❐
Clock alarm with programmable interrupts
❐
Capacitor or battery backup for RTC
❐
Backup current of 0.35 µA (typical)
High-speed serial peripheral interface (SPI)
❐
40-MHz clock rate – SRAM memory access
❐
25-MHz clock rate – RTC memory access
❐
Supports SPI mode 0 (0,0) and mode 3 (1,1)
■
Logic Block Diagram
V
CC
V
CAP
CS
WP
SCK
HOLD
Instruction decode
Write protect
Control logic
QuantumTrap
32 K X 8
Power Control
SRAM Array
32 K X 8
STORE
RECALL
STORE/RECALL
Control
HSB
Instruction
register
A0-A14
Address
Decoder
D0-D7
RTC
X
out
X
in
INT
MUX
SI
Data I/O register
SO
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation
Document Number: 001-53881 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 27, 2013
Not Recommended for New Designs
256-Kbit nonvolatile static random access memory (nvSRAM)
❐
Internally organized as 32 K × 8
❐
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by user using
HSB pin (Hardware STORE) or SPI instruction (Software
STORE)
❐
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
❐
Automatic STORE on power-down with a small capacitor
Write protection
❐
Hardware protection using Write Protect (WP) pin
❐
Software protection using Write Disable instruction
❐
Software block protection for 1/4, 1/2, or entire array
Low power consumption
❐
Single 3 V +20%, –10% operation
❐
Average active current of 10 mA at 40 MHz operation
Industry standard configurations
❐
Industrial temperature
❐
16-pin small outline integrated circuit (SOIC) package
❐
Restriction of hazardous substances (RoHS) compliant
■
■
CY14B256P
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Device Operation .............................................................. 4
SRAM Write ................................................................. 4
SRAM Read ................................................................ 4
STORE Operation ....................................................... 4
AutoStore Operation .................................................... 4
Software STORE Operation ........................................ 5
Hardware STORE and HSB Pin Operation ................. 5
RECALL Operation ...................................................... 5
Hardware RECALL (Power-Up) .................................. 5
Software RECALL ....................................................... 5
Disabling and Enabling AutoStore ............................... 5
Serial Peripheral Interface ............................................... 6
SPI Overview ............................................................... 6
SPI Modes ......................................................................... 7
SPI Operating Features .................................................... 8
Power-Up .................................................................... 8
Power On Reset .......................................................... 8
Power-Down ................................................................ 8
Active Power and Standby Power Modes ................... 8
SPI Functional Description .............................................. 8
Status Register ................................................................. 9
Read Status Register (RDSR) Instruction ................... 9
Write Status Register (WRSR) Instruction .................. 9
Write Protection and Block Protection ......................... 10
Write Enable (WREN) Instruction .............................. 10
Write Disable (WRDI) Instruction .............................. 11
Block Protection ........................................................ 11
Hardware Write Protection (WP Pin) ......................... 11
Memory Access .............................................................. 12
Read Sequence (READ) instruction .......................... 12
Write Sequence (WRITE) instruction ........................ 12
RTC Access ..................................................................... 14
READ RTC (RDRTC) Instruction .............................. 14
WRITE RTC (WRTC) Instruction ............................... 14
nvSRAM Special Instructions ........................................ 15
Software STORE (STORE) instruction ...................... 15
Software RECALL (RECALL) instruction .................. 15
AutoStore Enable (ASENB) instruction ..................... 15
AutoStore Disable (ASDISB) instruction ................... 16
HOLD Pin Operation ................................................. 16
Real Time Clock Operation ............................................ 17
nvTime Operation ...................................................... 17
Clock Operations ....................................................... 17
Reading the Clock ..................................................... 17
Setting the Clock ....................................................... 17
Backup Power ........................................................... 17
Stopping and Starting the Oscillator .......................... 17
Calibrating the Clock ................................................. 18
Alarm ......................................................................... 18
Watchdog Timer ........................................................ 18
Power Monitor ........................................................... 19
Interrupts ................................................................... 19
Flags Register ........................................................... 19
Accessing the Real Time Clock through SPI ............. 20
Maximum Ratings ........................................................... 25
Operating Range ............................................................. 25
DC Electrical Characteristics ........................................ 25
Data Retention and Endurance ..................................... 26
Capacitance .................................................................... 26
Thermal Resistance ........................................................ 26
AC Test Loads and Waveforms ..................................... 26
AC Test Conditions ........................................................ 26
RTC Characteristics ....................................................... 27
AC Switching Characteristics ....................................... 27
Switching Waveforms .................................................... 28
AutoStore or Power-Up RECALL .................................. 29
Switching Waveforms .................................................... 29
Software Controlled STORE/RECALL Cycles .............. 30
Switching Waveforms .................................................... 30
Hardware STORE Cycle ................................................. 31
Switching Waveforms .................................................... 31
Ordering Information ...................................................... 32
Ordering Code Definitions ......................................... 32
Package Diagram ............................................................ 33
Acronyms ........................................................................ 34
Document Conventions ................................................. 34
Units of Measure ....................................................... 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 37
Worldwide Sales and Design Support ....................... 37
Products .................................................................... 37
PSoC Solutions ......................................................... 37
Document Number: 001-53881 Rev. *J
Page 2 of 37
Not Recommended for New Designs
CY14B256P
Pinouts
Figure 1. 16-pin SOIC pinout
NC
VRTCbat
Xout
Xin
WP
HOLD
V
RTCcap
V
SS
1
2
3
4
5
6
7
8
Top View
not to scale
12
11
10
9
SI
16
15
14
13
V
CC
INT
V
CAP
SO
CS
HSB
Pin Definitions
Pin Name
CS
SCK
SI
SO
WP
HOLD
HSB
I/O Type
Input
Input
Input
Output
Input
Input
Description
Chip select.
Activates the device when pulled LOW. Driving this pin HIGH puts the device in low power
standby mode.
Serial clock.
Runs at speeds up to maximum of f
SCK
. Serial input is latched at the rising edge of this
clock. Serial output is driven at the falling edge of the clock.
Serial input.
Pin for input of all SPI instructions and data.
Serial output.
Pin for output of data through SPI.
Write protect.
Implements hardware write protection in SPI.
HOLD pin.
Suspends serial operation.
Input/output
Hardware STORE busy:
Output: Indicates busy status of nvSRAM when LOW. After each hardware and software STORE
operation HSB is driven HIGH for a short time (t
HHHD
) with standard output high current and then a weak
internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection optional).
Input: Hardware STORE implemented by pulling this pin LOW externally.
Power supply
AutoStore capacitor.
Supplies power to the nvSRAM during power loss to STORE data from the SRAM
to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It must never
be connected to ground.
V
CAP
V
RTCcap[2]
Power supply
Capacitor backup for RTC.
Left unconnected if V
RTCbat
is used.
V
RTCbat[2]
Power supply
Battery backup for RTC.
Left unconnected if V
RTCcap
is used.
Xout
[2]
Xin
[2]
INT
[2]
Output
Input
Output
No connect
Crystal output connection.
Drives crystal on start up.
Crystal input connection.
For 32.768 kHz crystal.
Interrupt output.
Programmable to respond to the clock alarm, the watchdog timer, and the power
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).
No connect.
This pin is not connected to the die.
NC
V
SS
V
CC
Power supply
Ground
Power supply
Power supply (2.7 V to 3.6 V)
Note
2. Left unconnected if RTC feature is not used.
Document Number: 001-53881 Rev. *J
Page 3 of 37
Not Recommended for New Designs
SCK
CY14B256P
Device Operation
CY14B256P is a 256-Kbit nvSRAM memory with integrated RTC
and SPI interface. All the reads and writes to nvSRAM happen
to the SRAM which gives nvSRAM the unique capability to
handle infinite writes to the memory. The data in SRAM is
secured by a STORE sequence that transfers the data in parallel
to the nonvolatile QuantumTrap cells. A small capacitor (V
CAP
)
is used to AutoStore the SRAM data in nonvolatile cells when
power goes down providing power-down data security. The
QuantumTrap nonvolatile elements built in the reliable SONOS
technology make nvSRAM the ideal choice for secure data
storage.
In CY14B256P, the 256-Kbit memory array is organized as
32 K words × 8 bits. The memory is accessed through a standard
SPI interface that enables very high clock speeds up to 40 MHz
with zero cycle delay read and write cycles. CY14B256P
supports SPI modes 0 and 3 (CPOL, CPHA = 0, 0 and 1, 1) and
operates as SPI slave. The device is enabled using the chip
select (CS) pin and accessed through serial input (SI), serial
output (SO), and serial clock (SCK) pins.
CY14B256P provides the feature for hardware and software
write protection through the WP pin and WRDI instruction.
CY14B256P also provides mechanisms for block write
protection (quarter, half, or full array) using BP0 and BP1 pins in
the Status Register. Further, the HOLD pin is used to suspend
any serial communication without resetting the serial sequence.
CY14B256P uses the standard SPI opcodes for memory access.
In addition to the general SPI instructions for read and write,
CY14B256P provides four special instructions that allow access
to four nvSRAM specific functions: STORE, RECALL, AutoStore
Disable (ASDISB), and AutoStore Enable (ASENB).
The major benefit of nvSRAM over serial EEPROMs is that all
reads and writes to nvSRAM are performed at the speed of SPI
bus with zero cycle delay. Therefore, no wait time is required
after any of the memory accesses. The STORE and RECALL
operations need finite time to complete and all memory accesses
are inhibited during this time. While a STORE or RECALL
operation is in progress, the busy status of the device is indicated
by the Hardware STORE Busy (HSB) pin and also reflected on
the RDY bit of the Status Register.
SRAM Read
A read cycle in CY14B256P is performed at the SPI bus speed
and the data is read out with zero cycle delay after the READ
instruction is executed. The READ instruction is issued through
the SI pin of the nvSRAM and consists of the READ opcode and
two bytes of address. The data is read out on the SO pin.
CY14B256P allows burst mode reads to be performed through
SPI. This enables reads on consecutive addresses without
issuing a new READ instruction. When the last address in
memory is reached in burst mode read, the address rolls over to
0x0000 and the device continues to read.
The SPI read cycle sequence is defined in the
Memory Access
section of SPI Protocol Description.
STORE operation transfers the data from the SRAM to the
nonvolatile QuantumTrap cells. The CY14B256P STOREs data
to the nonvolatile cells using one of the three STORE operations:
AutoStore, activated on device power-down; Software STORE,
activated by a STORE instruction; and Hardware STORE,
activated by the HSB. During the STORE cycle, an erase of the
previous nonvolatile data is first performed, followed by a
program of the nonvolatile elements. After a STORE cycle is
initiated, read/write to CY14B256P is inhibited until the cycle is
completed.
The HSB signal or the RDY bit in the Status Register can be
monitored by the system to detect if a STORE or Software
RECALL cycle is in progress. The busy status of nvSRAM is
indicated by HSB being pulled LOW or RDY bit being set to ‘1’.
To avoid unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place since the most recent STORE or
RECALL cycle. However, software initiated STORE cycles are
performed regardless of whether a write operation has taken
place.
AutoStore Operation
The AutoStore operation is a unique feature of nvSRAM which
automatically stores the SRAM data to QuantumTrap cells
during power-down. This STORE makes use of an external
capacitor (V
CAP
) and enables the device to safely STORE the
data in the nonvolatile memory when power goes down.
During normal operation, the device draws current from V
CC
to
charge the capacitor connected to the V
CAP
pin. When the
voltage on the V
CC
pin drops below V
SWITCH
during power-down,
the device inhibits all memory accesses to nvSRAM and
automatically performs a conditional STORE operation using the
charge from the V
CAP
capacitor. The AutoStore operation is not
initiated if no write cycle was performed since the last RECALL.
Note
If a capacitor is not connected to V
CAP
pin, AutoStore must
be disabled by issuing the AutoStore Disable instruction
specified in
AutoStore Enable (ASENB) instruction on page 15.
If AutoStore is enabled without a capacitor on V
CAP
pin, the
device attempts an AutoStore operation without sufficient charge
to complete the store. This corrupts the data stored in the
nvSRAM and Status Register. To resume normal functionality,
the WRSR instruction must be issued to update the nonvolatile
bits BP0, BP1 and WPEN in the Status Register.
SRAM Write
All writes to nvSRAM are carried out on the SRAM and do not
use up any endurance cycles of the nonvolatile memory. This
enables the user to perform infinite write operations. A write cycle
is performed through the WRITE instruction. The WRITE
instruction is issued through the SI pin of the nvSRAM and
consists of the WRITE opcode, two bytes of address, and one
byte of data. Write to nvSRAM is done at SPI bus speed with zero
cycle delay.
CY14B256P allows burst mode writes to be performed through
SPI. This enables write operations on consecutive addresses
without issuing a new WRITE instruction. When the last address
in memory is reached in burst mode, the address rolls over to
0x0000 and the device continues to write.
The SPI write cycle sequence is defined in the
Memory Access
section of SPI Protocol Description.
Document Number: 001-53881 Rev. *J
Page 4 of 37
Not Recommended for New Designs
STORE Operation
CY14B256P
Figure 2
shows the proper connection of the storage capacitor
(V
CAP
) for AutoStore operation. Refer to
DC Electrical
Characteristics on page 25
for the size of the V
CAP
.
Figure 2. AutoStore Mode
V
CC
Note
For successful last data byte STORE, a hardware store
should be initiated atleast one clock cycle after the last data bit
D0 is received.
Upon completion of the STORE operation, the nvSRAM memory
access is inhibited for t
LZHSB
time after HSB pin returns HIGH.
The HSB pin must be left unconnected if not used.
0.1 uF
10 kOhm
V
CC
RECALL Operation
A RECALL operation transfers the data stored in the nonvolatile
QuantumTrap elements to the SRAM. In CY14B256P, a
RECALL may be initiated in two ways: Hardware RECALL,
initiated on power-up; and Software RECALL, initiated by a SPI
RECALL instruction.
V
CAP
V
CAP
V
SS
Hardware RECALL (Power-Up)
During power-up, when V
CC
crosses V
SWITCH
, an automatic
RECALL sequence is initiated, which transfers the content of
nonvolatile memory on to the SRAM.
Software STORE Operation
Software STORE allows the user to trigger a STORE operation
through a special SPI instruction. STORE operation is initiated
by executing STORE instruction irrespective of whether a write
has been performed since the last NV operation.
A STORE cycle takes t
STORE
time to complete, during which all
the memory accesses to nvSRAM are inhibited. The RDY bit of
the Status Register or the HSB pin may be polled to find the
Ready/Busy status of the nvSRAM. After the t
STORE
cycle time
is completed, the SRAM is activated again for read and write
operations.
A Power-Up RECALL cycle takes t
FA
time to complete and the
memory access is disabled during this time. HSB pin is used to
detect the Ready status of the device.
Software RECALL
Software RECALL allows the user to initiate a RECALL operation
to restore the content of nonvolatile memory on to the SRAM. In
CY14B256P, this can be done by issuing a RECALL instruction
in SPI.
A Software RECALL takes t
RECALL
time to complete during
which all memory accesses to nvSRAM are inhibited. The
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Hardware STORE and HSB Pin Operation
The HSB pin in CY14B256P is used to control and acknowledge
STORE operations. If no STORE/RECALL is in progress, this pin
can be used to request a Hardware STORE cycle. When the
HSB pin is driven LOW, the CY14B256P conditionally initiates a
STORE operation after t
DELAY
duration. An actual STORE cycle
starts only if a write to the SRAM is performed since the last
STORE or RECALL cycle. Reads and writes to the memory are
inhibited for t
STORE
duration or as long as HSB pin is LOW.
The HSB pin also acts as an open drain driver (internal 100 k
weak pull-up resistor) that is internally driven LOW to indicate a
busy condition when the STORE (initiated by any means) is in
progress.
Note
After each Hardware and Software STORE operation HSB
is driven HIGH for a short time (t
HHHD
) with standard output high
current and then remains HIGH by an internal 100 k pull-up
resistor.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled in CY14B256P by using the ASDISB instruction. If
this is done, the nvSRAM does not perform a STORE operation
at power-down.
Note
CY14B256P comes from the factory with AutoStore
Enabled and 0x00 written in all cells.
AutoStore can be re-enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if the user
needs this setting to survive the power cycle, a STORE operation
must be performed following AutoStore Disable or Enable
operation.
Note
If AutoStore is disabled and V
CAP
is not required, then the
V
CAP
pin must be left open. The V
CAP
pin must never be
connected to ground. The power-up RECALL operation cannot
be disabled in any case.
Document Number: 001-53881 Rev. *J
Page 5 of 37
Not Recommended for New Designs
CS
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. All memory accesses are inhibited while a RECALL
cycle is in progress. The RECALL operation does not alter the
data in the nonvolatile elements.
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