PRoC™ - CapSense
PRoC™ - CapSense
®
CYRF89435
®
PRoC-CS Features
■
❐
■
In-system serial programming (ISSP)
Single Device, Two functions
❐
8-bit flash based CapSense controller MCU function and
2.4-GHz WirelessUSB™ NL radio transceiver function in a
single device
Wide operating range: 1.9 V to 3.6 V
❐
Configurable capacitive sensing elements
❐
7
μA
per sensor at 500 ms scan rate
❐
Supports SmartSense™ Auto-tuning
®
❐
Supports a combination of CapSense buttons, sliders, and
proximity sensors
❐
SmartSense_EMC offers superior noise immunity for
applications with challenging conducted and radiated noise
conditions
RF Attributes
❐
2.4-GHz WirelessUSB-NL Transceiver function
❐
Operates in the 2.4-GHz ISM Band (2.402 GHz - 2.479 GHz)
❐
1-Mbps over-the-air data rate
❐
Receive sensitivity typical: –87 dBm
❐
1
μA
typical current consumption in sleep state
❐
Closed-loop frequency synthesis
❐
Supports frequency-hopping spread spectrum
❐
On-chip packet framer with 64-byte first in first out (FIFO)
data buffer
❐
Built-in auto-retry-acknowledge protocol simplifies usage
❐
Built-in cyclic redundancy check (CRC), forward error
correction (FEC), data whitening
❐
Additional outputs for interrupt request (IRQ) generation
❐
Digital readout of received signal strength indication (RSSI)
MCU Attributes
❐
Powerful Harvard-architecture processor
❐
M8C CPU – Up to 4 MIPS with 24 MHz Internal clock, external
crystal resonator or clock signal
❐
Low power at high speed
Temperature range: 0 °C to +70 °C
Flexible on-chip memory
• 32 KB Flash/2 KB SRAM
❐
50,000 flash erase/write cycles
❐
Partial flash updates
❐
Flexible protection modes
■
Precision, programmable clocking
❐
Internal main oscillator (IMO): 6/12/24 MHz ± 5%
❐
Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep timers
❐
Precision 32 kHz oscillator for optional external crystal
Programmable pin configurations
❐
Up to 13 general-purpose I/Os (GPIOs)
❐
Dual mode GPIO: All GPIOs support digital I/O and analog
inputs
❐
25-mA sink current on each GPIO
• 120 mA total sink current on all GPIOs
❐
Pull-up, high Z, open-drain modes on all GPIOs
❐
CMOS drive mode –5 mA source current on ports 0 and 1
and 1 mA on port 2
❐
20 mA total source current on all GPIOs
Versatile analog system
❐
Low-dropout voltage regulator for all analog resources
❐
Common internal analog bus enabling capacitive sensing on
all pins
❐
High power supply rejection ratio (PSRR) comparator
❐
8 to 10-bit incremental analog-to-digital converter (ADC)
Additional system resources
2
❐
I C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
❐
SPI master and slave: Configurable 46.9 kHz to 12 MHz
❐
Three 16-bit timers
❐
Watchdog and sleep timers
❐
Integrated supervisory circuit
❐
Emulated E2PROM using flash memory
Complete development tools
❐
Free development tool (PSoC Designer™)
❐
Full-featured, in-circuit emulator (ICE) and programmer
❐
Full-speed emulation
❐
Complex breakpoint structure
❐
128 KB trace memory
Package option
❐
40-pin 6 mm × 6 mm QFN
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Cypress Semiconductor Corporation
Document Number: 001-76581 Rev. *E
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 15, 2013
CYRF89435
Logical Block Diagram
Port 2
Port 1
Port 0
Prog. LDO
PWR Sys
(Regulator)
PSoC Core
System Bus
Global Analog Connect
SRAM
2048 Bytes
Interrupt
Controller
SROM
32K Flash
Sleep and
Watchdog
CPU Core
(M8C)
6/12/24 MHz Internal Main Oscillator
Internal Low Speed Oscillator (ILO
Multiple Clock Sources
CapSense
System
CapSense
CapS
Module
Analog
Reference
Two
Comparators
Analog Mux
V
IN
V
DD_IO
V
OUT
LDO Linear
Regulator
PKT
FIFO
GFSK
Modulator
WIRELESSUSB-NL
SYSTEM
PA
SPI Registers
Framer
Synthesizer
VCO
ANT
ANTb
RST
_n
Pwr Reset
/
BRCLK
Xtal Osc
GFSK
Demodulator
X
Image
Rej . Mxr
.
LNA + BPF
XTALi
XTALo
I2C Slave
Internal Voltage
References
System
Resets
SPI
Master/
Slave
Three 16 bit
Timers
POR
and
LVD
Digital
Clocks
SYSTEM RESOURCES
Document Number: 001-76581 Rev. *E
Page 2 of 39
CYRF89435
Contents
PSoC
®
Functional Overview ............................................ 4
PSoC Core .................................................................. 4
CapSense System ....................................................... 4
WirelessUSB-NL System ............................................ 5
Transmit Power Control ............................................... 5
Power-on and Register Initialization Sequence ........... 5
Getting Started .................................................................. 6
CapSense Design Guides ........................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pinouts .............................................................................. 9
Pin Definitions ................................................................ 10
Electrical Specifications – PSoC Core ......................... 11
Absolute Maximum Ratings ....................................... 11
Operating Temperature ............................................. 11
DC Chip-Level Specifications .................................... 12
DC GPIO Specifications ............................................ 13
Analog DC Mux Bus Specifications ........................... 14
DC Low Power Comparator Specifications ............... 14
Comparator User Module Electrical Specifications ... 15
ADC Electrical Specifications .................................... 16
DC POR and LVD Specifications .............................. 17
DC Programming Specifications ............................... 17
DC I2C Specifications ............................................... 18
DC Reference Buffer Specifications .......................... 18
DC IDAC Specifications ............................................ 18
AC Chip-Level Specifications .................................... 19
AC GPIO Specifications ............................................ 20
AC Comparator Specifications .................................. 21
AC External Clock Specifications .............................. 21
AC Programming Specifications ................................ 22
AC I2C Specifications ................................................ 23
SPI Master AC Specifications ................................... 24
SPI Slave AC Specifications ..................................... 25
Electrical Specifications – RF Section ......................... 27
Initialization Timing Requirements ............................ 30
SPI Timing Requirements ......................................... 31
Packaging Information ................................................... 32
Thermal Impedances ................................................. 33
Capacitance on Crystal Pins ..................................... 33
Solder Reflow Specifications ..................................... 33
Development Tool Selection ......................................... 34
Software .................................................................... 34
Development Kits ...................................................... 34
Device Programmers ................................................. 34
Ordering Information ...................................................... 35
Ordering Code Definitions ......................................... 35
Acronyms ........................................................................ 36
Reference Documents .................................................... 36
Document Conventions ................................................. 36
Units of Measure ....................................................... 36
Numeric Naming ........................................................ 37
Glossary .......................................................................... 37
Document History Page ................................................. 38
Sales, Solutions, and Legal Information ...................... 39
Worldwide Sales and Design Support ....................... 39
Products .................................................................... 39
PSoC Solutions ......................................................... 39
Document Number: 001-76581 Rev. *E
Page 3 of 39
CYRF89435
PSoC
®
Functional Overview
The PSoC family consists of on-chip controller devices, which
are designed to replace multiple traditional microcontroller unit
(MCU)-based components with one, low cost single-chip
programmable component. A PSoC device includes
configurable analog and digital blocks, and programmable
interconnect. This architecture allows the user to create
customized peripheral configurations, to match the requirements
of each individual application. Additionally, a fast CPU, flash
program memory, SRAM data memory, and configurable I/O are
included in a range of convenient pinouts.
The architecture for this device family, as shown in the
Logical
Block Diagram on page 2,
consists of three main areas:
■
■
■
■
from prototyping to mass production without re-tuning for
manufacturing variations in PCB and/or overlay material
properties.
SmartSense_EMC
In addition to the SmartSense auto-tuning algorithm to remove
manual tuning of CapSense applications, SmartSense_EMC
user module incorporates a unique algorithm to improve
robustness of capacitive sensing algorithm/circuit against high
frequency conducted and radiated noise. Every electronic device
must comply with specific limits for radiated and conducted
external noise and these limits are specified by regulatory bodies
(for example, FCC, CE, U/L and so on). A very good PCB layout
design, power supply design and system design is a mandatory
for a product to pass the conducted and radiated noise tests. An
ideal PCB layout, power supply design or system design is not
often possible because of cost and form factor limitations of the
product. SmartSense_EMC with superior noise immunity is well
suited and handy for such applications to pass radiated and
conducted noise test.
Figure 1. CapSense System Block Diagram
CS1
The Core
CapSense Analog System
WirelessUSB-NL System
System Resources.
A common, versatile bus allows connection between I/O and the
analog system.
Each CYRF89435 device includes a dedicated CapSense block
that provides sensing and scanning control circuitry for
capacitive sensing applications. The 13 GPIOs provide access
to the MCU and analog mux.
IDAC
Analog Global Bus
CS2
PSoC Core
The PSoC Core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and IMO and
ILO. The CPU core, called the M8C, is a powerful processor with
speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit
Harvard-architecture microprocessor.
Vr
Reference
Buffer
CSN
Cinternal
CapSense System
The analog system contains the capacitive sensing hardware.
Several hardware algorithms are supported. This hardware
performs capacitive sensing and scanning without requiring
external components. The analog system is composed of the
CapSense PSoC block and an internal 1 V or 1.2 V analog
reference, which together support capacitive sensing of up to
13 inputs. Capacitive sensing is configurable on each GPIO pin.
Scanning of enabled CapSense pins are completed quickly and
easily across multiple ports.
SmartSense
SmartSense is an innovative solution from Cypress that removes
manual tuning of CapSense applications. This solution is easy to
use and provides a robust noise immunity. It is the only
auto-tuning solution that establishes, monitors, and maintains all
required tuning parameters. SmartSense allows engineers to go
IMO
Comparator
Mux
Mux
Cexternal (P0[1]
or P0[3])
Refs
Cap Sense Counters
CSCLK
CapSense
Clock Select
Oscillator
Document Number: 001-76581 Rev. *E
Page 4 of 39
CYRF89435
On-chip transmit and receive FIFO registers are available to
buffer the data transfer with MCU. Over-the-air data rate is
always 1 Mbps even when connected to a slow, low-cost MCU.
Built-in CRC, FEC, data whitening, and automatic
retry/acknowledge are all available to simplify and optimize
performance for individual applications.
For more details on the radio’s implementation details and timing
requriements, please go through the WirelessUSB-NL datasheet
in
www.cypress.com.
Figure 2. WirelessUSB-NL logic Block Diagram
V
IN
V
DD_IO
V
OUT
V
DD1
...V
DD7
Analog Multiplexer System
The Analog Mux Bus can connect to every GPIO pin. Pins are
connected to the bus individually or in any combination. The bus
also connects to the analog system for analysis with the
CapSense block comparator.
Switch control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■
■
■
Complex capacitive sensing interfaces, such as sliders and
touchpads.
Chip-wide mux that allows analog input from any I/O pin.
Crosspoint connection between any I/O pin combinations.
LDO Linear
Regulator
PKT
GFSK
Modulator
PA
WirelessUSB-NL, optimized to operate in the 2.4-GHz ISM band,
is Cypress's third generation of 2.4-GHz low-power RF
technology. WirelessUSB-NL implements a Gaussian
frequency-shift keying (GFSK) radio using a differentiated
single-mixer, closed-loop modulation design that optimizes
power efficiency and interference immunity. Closed-loop
modulation effectively eliminates the problem of frequency drift,
enabling WirelessUSB-NL to transmit up to 255-byte payloads
without repeatedly having to pay power penalties for re-locking
the phase-locked loop (PLL) as in open-loop designs
Among the advantages of WirelessUSB-NL are its fast lock times
and channel switching, along with the ability to transmit larger
payloads. Use of longer payload packets, compared to multiple
short payload packets, can reduce overhead, improve overall
power efficiency, and help alleviate spectrum crowding.
Combined with Cypress's Capacitive touch sense controllers,
WirelessUSB-NL also provides the lowest bill of materials (BOM)
cost solution for sophisticated PC peripheral applications such
as wireless keyboards and mice, as well as best-in-class
wireless performance in other demanding applications. such as
toys, remote controls, fitness, automation, presenter tools, and
gaming.
With PRoC-CS, the WirelessUSB-NL transceiver can add
wireless capability to a wide variety of CapSense applications.
The WirelessUSB-NL is a fully-integrated CMOS RF transceiver,
GFSK data modem, and packet framer, optimized for use in the
2.4-GHz ISM band. It contains transmit, receive, RF synthesizer,
and digital modem functions, with few external components. The
transmitter supports digital power control. The receiver uses
extensive digital processing for excellent overall performance,
even in the presence of interference and transmitter
impairments.
The product transmits GFSK data at approximately 0-dBm
output power. Sigma-Delta PLL delivers high-quality DC-coupled
transmit data path.
The low-IF receiver architecture produces good selectivity and
image rejection, with typical sensitivity of –87 dBm or better on
most channels. Sensitivity on channels that are integer multiples
of the crystal reference oscillator frequency (12 MHz) may show
approximately 5 dB degradation. Digital RSSI values are
available to monitor channel quality.
Framer
SPI_SS
CLK
MISO
MOSI
RST_n
SPI Registers
WirelessUSB-NL System
Synthesizer
VCO
ANT
ANTb
Pwr/ Reset
BRCLK
Xtal Osc
GFSK
Demodulator
X
Image
Rej. Mxr.
LNA + BPF
XTALi
XTALo
GND GND
Transmit Power Control
The following table lists recommended settings for register 9 for
short-range applications, where reduced transmit RF power is a
desirable trade off for lower current.
Table 1. Transmit Power Control
Power Setting
Description
PA0 - Highest power
PA2 - High power
PA4 - High power
PA8 - Low power
PA12 - Lower power
Typical
Transmit
Power
(dBm)
+1
0
–3
–7.5
–11.2
Value of Register 9
Silicon ID
0x1002
0x1820
0x1920
0x1A20
0x1C20
0x1E20
Silicon ID
0x2002
0x7820
0x7920
0x7A20
0x7C20
0x7E20
Note: Silicon ID can be read from Register 31.
Power-on and Register Initialization Sequence
For proper initialization at power up, V
IN
must ramp up at the
minimum overall ramp rate no slower than shown by T
VIN
specification in the following figure. During this time, the RST_n
line must track the V
IN
voltage ramp-up profile to within
approximately 0.2 V. Since most MCU GPIO pins automatically
default to a high-Z condition at power up, it only requires a pull-up
resistor. When power is stable and the MCU POR releases, and
MCU begins to execute instructions, RST_n must then be pulsed
low as shown in
Figure 13 on page 31,
followed by writing Reg[27
= 0x4200. During or after this SPI transaction, the State Machine
status can be read to confirm FRAMER_ST= 1, indicating a
proper initialization.
Page 5 of 39
Document Number: 001-76581 Rev. *E
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