TSM2N7002
60V N-Channel Enhancement Mode MOSFET
Pin assignment:
1. Gate
2. Source
3. Drain
V
DS
= 60V
R
DS (on)
, Vgs @ 10V, Ids @ 500mA = 7.5Ω
R
DS (on)
, Vgs @ 5V, Ids @ 50mA = 13.5Ω
Features
Advanced trench process technology
High density cell design for low on-resistance
High input impedance
High speed switching
No minority carrier storage time
CMOS logic compatible input
No secondary breakdown
Compact and low profile SOT-23 package
Block Diagram
Ordering Information
Part No.
TSM2N7002CX
Packing
Tape & Reel
Package
SOT-23
Absolute Maximum Rating
(Ta = 25
o
C unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
Pulsed Drain Current
Maximum Power Dissipation
Ta = 25
o
C
Ta > 25 C
Operating Junction Temperature
Operating Junction and Storage Temperature Range
T
J
T
J
, T
STG
o
Symbol
V
DS
V
GS
I
D
I
DM
P
D
Limit
60
± 20
115
800
225
1.8
+150
- 55 to +150
Unit
V
V
mA
mA
mW
MW/ C
o
o
o
C
C
Thermal Performance
Parameter
Lead Temperature (1/8” from case)
Junction to Ambient Thermal Resistance (PCB mounted)
Note: Surface mounted on FR4 board t<=5sec.
Symbol
T
L
R
θja
Limit
5
417
Unit
S
o
C/W
TSM2N7002
1-3
2003/12 rev. B
Electrical Characteristics
Tj = 25 C unless otherwise noted
o
Parameter
Static
Drain-Source Breakdown Voltage
Drain-Source On-State Resistance
Drain-Source On-State Resistance
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage
On-State Drain Current
Conditions
V
GS
= 0V, I
D
= 10uA
V
GS
= 10V, I
D
= 500mA
V
GS
= 5V, I
D
= 50mA
V
DS
= V
GS
, I
D
= 250uA
V
DS
= 60V, V
GS
= 0V
V
GS
= ± 20V, V
DS
= 0V
V
DS
2V, V
GS
= 10V
Symbol
Min
60
--
--
1.0
--
--
500
Typ
--
--
--
--
--
--
--
Max
--
7.5
13.5
2.5
1.0
± 100
--
Unit
V
Ω
BV
DSS
R
DS(ON)
R
DS(ON)
V
GS(TH)
I
DSS
I
GSS
I
D(ON)
V
uA
nA
mA
Dynamic
Turn-On Rise Time
Turn-Off Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
V
DD
= 25V, R
L
= 50Ω,
I
D
= 500mA, V
GEN
= 10V,
R
G
= 25Ω
V
DS
= 25V, V
GS
= 0V,
f = 1.0MHz
t
r
t
f
C
iss
C
oss
C
rss
--
--
--
--
--
--
--
50
25
5
20
40
--
--
--
pF
nS
Source-Drain Diode
Max. Diode Forward Current
Diode Forward Voltage
I
S
= 115mA, V
GS
= 0V
Note : pulse test: pulse width <=300uS, duty cycle <=2%
I
S
V
SD
--
--
--
1.3
115
1.5
mA
V
TSM2N7002
2-3
2003/12 rev. B
FPGA/CPLD
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