TSM7104D
20V Dual P-Channel Enhancement Mode MOSFET
Pin assignment:
1. Source 1
2. Gate 1
3. Source 2
4. Gate 2
5, 6. Drain 2
7, 8. Drain 1
V
DS
= - 20V
R
DS (on)
, Vgs @ - 4.5V, Ids @ - 2.3A =130mΩ
R
DS (on)
, Vgs @ - 2.5V, Ids @ - 2.0A =190mΩ
Features
Advanced trench process technology
High density cell design for ultra low on-resistance
Excellent thermal and electrical capabilities
Surface mount
Fast switching
Block Diagram
Ordering Information
Part No.
TSM7104DCS
Packing
Tape & Reel
Package
SOP-8
Absolute Maximum Rating
(Ta = 25
o
C
unless otherwise noted)
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current, V
GS
@4.5V.
Pulsed Drain Current, V
GS
@4.5V
Maximum Power Dissipation
Ta = 25
o
C
Ta > 25 C
Operating Junction Temperature
Operating Junction and Storage Temperature Range
T
J
T
J
, T
STG
o
Symbol
V
DS
V
GS
I
D
I
DM
P
D
Limit
- 20V
±8
- 2.3
- 10
2
16
+150
- 55 to +150
Unit
V
V
A
A
W
mW/ C
o
o
o
C
C
Thermal Performance
Parameter
Junction to Ambient Thermal Resistance (PCB mounted)
Note: Surface mounted on FR4 board t<=5sec.
Symbol
R
θja
Limit
62.5
Unit
o
C/W
TSM7104D
1-3
2003/12 rev. A
Electrical Characteristics
Rate I
D
= - 2.3A, (Ta = 25 C unless otherwise noted)
o
Parameter
Static
Drain-Source Breakdown Voltage
Drain-Source On-State
Resistance
Drain-Source On-State
Resistance
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate Body Leakage
Forward Transconductance
Conditions
Symbol
Min
Typ
Max
Unit
V
GS
= 0V, I
D
= - 250uA
V
GS
= - 4.5V, I
D
= -2.3A
V
GS
= - 2.5V, I
D
= -2.0A
V
DS
= V
GS
, I
D
= - 250uA
V
DS
= - 16V, V
GS
= 0V
V
GS
= ± 8V, V
DS
= 0V
V
DS
= - 5V, I
D
= - 2.3A
V
DS
= - 6V, I
D
= - 2.3A,
V
GS
= - 4.5V
V
DD
= - 6V, R
L
= 6Ω,
I
D
= - 1A, V
GEN
= - 4.5V,
R
G
= 6Ω
V
DS
= - 6V, V
GS
= 0V,
f = 1.0MHz
BV
DSS
R
DS(ON)
R
DS(ON)
V
GS(TH)
I
DSS
I
GSS
g
fs
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
C
iss
C
oss
C
rss
I
S
- 20
--
--
- 0.45
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
90
120
--
--
--
6.5
5.4
0.8
1.1
5
19
95
65
447
127
80
--
- 0.8
--
130
V
mΩ
190
--
- 1.0
± 100
--
10
--
--
25
60
110
80
--
--
--
- 1.6
- 1.2
A
V
pF
nS
nC
V
uA
nA
S
Dynamic
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Source-Drain Diode
Max. Diode Forward Current
Diode Forward Voltage
I
S
= - 1.6A, V
GS
= 0V
V
SD
Note : pulse test: pulse width <=300uS, duty cycle <=2%
TSM7104D
2-3
2003/12 rev. A
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