are packaged in a lead-free, 15x15 mm, 196-ball grid array for
space-saving installation. Built on Intel lead-free technology,
these controllers conform to the European Union’s Restrictions
on the use of Hazardous Substances (RoHS)
2
and Japan’s
White Goods Recycling Act.
Performance-enhancing features:
Each of the Intel
82573E/V/L controllers includes advanced interrupt-
handling features and uses efficient ring-buffer descriptor
data structures with on-chip caching for up to 64 packet
descriptors per queue. Other performance-enhancing
features include offloading tasks from the host via Transmission
Control Protocol/User Datagram Protocol/Internet Protocol
(TCP/UDP/IP) checksum calculations and TCP segmentation.
•
Controller Overview
Controller
82573E
82573E
82573V
82573V
82573L
82573L
Distinguishing Feature
Intel AMT
Lead-free
1
and Intel AMT
ASF 2.0 and APT
Lead-free, ASF 2.0, and APT
Low power
Lead-free and low power
®
Δ
Specifications: Intel
®
82573E/V/L Gigabit
Ethernet Controllers
Order Code
RC82573E
PC82573E
RC82573V
PC82573V
RC82573L
PC82573L
Electrical
Power supply
Typical targeted power
dissipation (82573E and
82573V only)
Typical targeted power
dissipation (82573L only)
•
3.3 V, 2.5 V, 1.2 V
•
•
•
•
•
•
•
•
1370 mW at 1000 Mbps active
535 mW at 100 Mbps active
592 mW at 10 Mbps active
177 mW at no link and no wake
1217 mW at 1000 Mbps active
483 mW at 100 Mbps active
504 mW at 10 Mbps active
53 mW at no link and no wake
Packaging
Operating temperature
Storage temperature
Package type
•
0° C to 70° C (maximum);
simplified thermal design
•
-40° C to 125° C
•
Lead-free
1
196-pin TF-BGA, 1.0 mm
ball pitch, 15x15 mm (simplifies LOM
board designs)
Features
PCI Express* Features
X1 PCIe* interface on Intel
®
I/O Controller Hub 7 (ICH7) or Memory
Control Hub (Intel
®
945/955 chipset) devices
2 Gbps peak bandwidth per direction
PCI Express Rev 1.0a specification
High bandwidth density per pin
Benefits
•
Bus sharing not required
•
Low-latency path to memory
•
Supports Gigabit Ethernet at wire speed
•
Standards interoperability
•
Provides PCIe power-management capabilities for PC and embedded applications
•
Less-congested board routing
Gigabit MAC/PHY Advanced Features
Wide, pipelined internal data path architecture
Optimized transmit (Tx) and receive (Rx) queues
32 KB configurable Rx and Tx first-in/first-out (FIFO)
IEEE 802.3x*-compliant flow-control support with software controllable
pause times and threshold values
Programmable host memory Rx buffers (256 B-16 KB)
Descriptor ring management hardware for Tx and Rx
Mechanism for reducing interrupts from Tx/Rx operations
Integrated PHY for 10/100/1000 Mbps (full- and half-duplex)
IEEE 802.3ab* auto-negotiation support
IEEE 802.3ab PHY compliance and compatibility
•
Low-latency data handling
•
Superior direct memory access (DMA) transfer rate performance
•
Network packet handling without waiting or buffer overflow
•
FIFO size adjustable to application
•
Reduce frame loss from Rx FIFO overruns
•
Hardware or software control over Tx of pause frames
•
Efficient use of system memory and PCIe bus
•
Simple software programming model
•
Maximizes system performance and throughput
•
Smaller footprint, lower power dissipation compared to multichip MAC and PHY solutions
•
Automatic link configuration for speed, duplex, flow control
•
Robust operation over installed base of Category-5 twisted-pair cabling
Host Offloading Features
Tx/Rx IP, TCP, and UDP checksum offloading
Tx TCP segmentation
IPv6 offloading
Advanced packet filtering
•
Lower CPU utilization
•
Increased throughput and lower CPU utilization
•
Compatible with large send offload (in Microsoft Windows* 2000)
•
Checksum and segmentation capability extended to new standard packet type
•
•
•
•
16 exact-matched packets (unicast or multicast)
4096-bit hash filter for multicast frames
Promiscuous (unicast and multicast) transfer mode support
Optional filtering of invalid frames
IEEE 802.1q* Virtual Local Area Network (VLAN) support with VLAN tag
insertion, stripping, and packet filtering for up to 4096 VLAN tags
Descriptor ring management hardware for Tx and Rx
•
Ability to create multiple VLAN segments
•
Optimized fetch and write-back mechanisms for efficient system memory and PCIe bandwidth usage
Manageability Features
Intel
®
Active Management Technology
Δ
(82573E only)
Out of Band (OOB) access allows remote management of PCs regardless of system power or OS state
Remote troubleshooting and recovery significantly reduces desk-side visits and increases IT efficiency
Proactive alerting and event logging decreases downtime and minimizes time to repair
Third-party non-volatile storage prevents users from removing critical inventory, remote control, or virus
protection agents
•
Remote HW and SW asset tracking eliminates time-consuming manual inventory tracking an reduces asset
accounting costs
•
•
•
•
•
One driver supports all Intel
®
PRO/1000 connections, simplifying installation and maintenance
•
Standard alerting capability to notify IT of system events
•
Filtering and redirection for external server Board Management Controller (BMC) data
•
Support for PXE ROMs integrated into the system BIOS
•
Remote network management through Desktop Management Interface (DMI) 2.0 and SNMP
•
Packet recognition and wake-up for LOM applications without software configuration
Intel
®
SingleDriver™ technology
Alerting Standards Format 2.0 (82573V only)
Advanced Pass Through (82573V only)
Boot ROM Preboot eXecution Environment (PXE) Flash interface support
SDG 3.0, WfM 3.0 and PC2001 compliant
Wake on LAN support
Additional Device Features Features
Three LED outputs
Programmable LED functionality
Internal phase-locked loop (PLL) for clock generation can use
25-MHz crystal
JTAG (IEEE 1149.1*) Test Access Port built in silicon
On-chip power control circuitry
Loop-back capabilities
SPI Flash or EEPROM support
Optional on-die voltage regulator
•
Provides the ability to display the various link, speed, and activity states of the LAN
•
Software definable function (speed, link, activity) and blinking allow flexible LED signaling implementations
•
Lower component count and reduced system cost
•
Simplified testing using boundary scan
•
Reduced number of on-board power supply regulators
•
Simplified power supply design for less power-critical applications
•
Allows OEMs to quickly check silicon integrity on their manufacturing line
•
Flexibility for external EEPROM or SPI Flash device to store LAN configuration data. SPI Flash may be shared
with system BIOS for reduced BOM cost.
•
Flexibility for an internal 2.5 V regulator for reduced BOM cost
For more information, contact your Intel sales representative.
1
Lead has not been intentionally added, but lead may still exist as an impurity below 1000 ppm.
Lead and other materials banned in the RoHS Directive are either (1) below all applicable substance thresholds as proposed by the EU or (2) an approved/pending exemption applies.
Intel
®
Active Management Technology requires a system with an Intel
®
945G Express Chipset, Intel
®
PRO/1000 PM network connection, and appropriate third-party software.
2
Δ
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL
PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY
WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products
are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice.
*Other names and brands may be claimed as the property of others.
Intel, the Intel logo, and Intel SingleDriver are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
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