Intel
®
82598EB 10 Gigabit Ethernet
Controller Datasheet
LAN Access Division
FEATURES
General
Serial Flash Interface
4-wire SPI EEPROM Interface
Configurable LED operation for software or OEM
customization of LED displays
Protected EEPROM space for private configuration
Device disable capability
Package Size - 31 x 31 mm
Networking
Complies with the 10 Gb/s and 1 Gb/s Ethernet/802.3ap
(KX/KX4) specification
Complies with the 10 Gb/s Ethernet/802.3ae (XAUI)
specification
Complies with the 1000BASE-BX specification
Support for jumbo frames of up to 16 kB
Auto negotiation clause 73 for supported mode
CX4 per 802.3ak
Flow control support: send/receive pause frames and
receive FIFO thresholds
Statistics for management and RMON
802.1q VLAN Support
TCP Segmentation Offload (TSO): up to 256 kB
IPv6 support for IP/TCP and IP/UDP receive checksum
offload
Fragmented UDP checksum offload for packet
reassembly
Message Signaled Interrupts (MSI)
Message Signaled Interrupts (MSI-X)
Interrupt throttling control to limit maximum interrupt
rate and improve CPU usage
Multiple receive queues (RSS) 8 x 8 and 16 x 4
32 transmit queues
Dynamic interrupt moderation
DCA support
TCP timer interrupts
No snoop
Relaxed ordering
Support for 16 Virtual Machines Device queues (VMDq)
per port
Host Interface
PCI Express* (PCIe*) Specification v2.0 (2.5 GT/s)
Bus width - x1, x2, x4, x8
64-bit address support for systems using more than
four GB of physical memory
MAC F
UNCTIONS
Descriptor ring management hardware for transmit and
receive
ACPI register set and power down functionality supporting D0
and D3 states
A mechanism for delaying/reducing transmit interrupts
Software-controlled global reset bit (resets everything except
the configuration registers)
Eight Software-Definable Pins (SDP) per port
Four of the SDP pins can be configured as general-purpose
interrupts
Wakeup
IPv6 wake-up filters
Configurable flexible filter (through EEPROM)
LAN function disable capability
Programmable receive buffer of 512 kB, which can be
subdivided to up-to-eight individual packet buffers
Programmable transmit buffer of 320 kB, subdivided into up-
to-eight individual packet buffers of 40 kB each
Default Configuration by EEPROM for all LEDs for pre-driver
functionality
Manageability
Eight VLAN L2 filters
16 Flex L3 Port filters
Four flexible TCO filters
Four L3 address filters (IPv4)
Advanced pass through-compatible management packet
transmit/receive support
SMBus interface to an external BMC
NC-SI interface to an external BMC
Four L3 address filters (IPv6)
Four L2 address filters
Revision: 3.23
September 2012
Intel
®
82598EB 10 GbE Controller - Legal
Legal
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS
OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL
ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO
SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
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PERSONAL INJURY OR DEATH MAY OCCUR.
Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not
rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities
arising from future changes to them. The information here is subject to change without notice. Do not finalize a
design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
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Copies of documents which have an order number and are referenced in this document, or other Intel literature,
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*Other names and brands may be claimed as the property of others.
Copyright © 2008, 2009, 2010; Intel Corporation. All Rights Reserved.
2
Intel
®
82598EB 10 GbE Controller - Revisions
Revisions
Rev
2.0
Date
12/08
•
•
Comments
Converted to single source using FrameMaker.
Updated internal/external pull-up/pull-down information.
2.2
February
2008
May 2008
Initial Release (Intel Public).
2.3
Updated sections/figures/tables: Product Features, 1.9.9, 2.2, 2.3, 2.9, 2.13, Table 2-17,
3.1.1.6, Table 3-17, 3.1.1.14.4, Note after Table 3-25, Device Cap, Device Control,
Device Status, Link CAP Lin Control, Link Status, tables in section 3.1.1.14.6, 3.1.3.1,
Figure 3-10, 3.2.1.2, 3.2.1.3, Table 3-38, Table 3-39, 3.2.3.2.5, Figure 3-12, Figure 3-
13, 3.3.2.3.1.7, Table 3-45, 3.4.3.1.1, 3.4.3.1.2, 3.4.3.4.2, 3.4.3.6.2, Figure 3-20,
Figure 3-21, Table 3-54, 3.5.2.4, 3.5.2.8, 3.5.2.10.1, 3.5.2.11, Table 3-59, Table 3-69,
3.5.3.3.2, 3.5.4.1, 3.5.4.2, Table 4-2, Table 4-4, 4.4.3.3.1 through 4.4.3.7, 4.4.3.3.12,
4.4.3.5.7 through 4.4.5.9, 4.4.3.6.2, 4.4.3.6.8, 4.4.3.6.11, 4.4.3.9, 4.4.3.11.1,
4.4.3.13.5, 4.4.3.13.8 through 4.4.3.13.10, 4.4.3.13.24, Table 5-7 through Table 5-10,
Table 5-12, and 5.6.4, 5.6.6.
Replaced Large Send Offload (LSO) with TCP Segmentation Offload (TSO).
Removed all references to “Header Replication”.
Updated reference schematics.
Updated Tables: 2-12, 2-14, 2-16, 3-17, 3-58, 3-71, 4-4, 5-3 through 5-5, 5-12, 5-15,
5-19,
Updated Section: 1.2, 1.8, 1.9.10, 2.13, 3.1.1.10.1, 3.1.1.14.2, 3.2.2.14.3.1,
3.1.1.14.4, 3.1.4.3.4, 3.2.1.3, 3.3.1.3.2, 3.3.1.4.1, 3.3.1.4.4.2, 3.4 through 3.4.4,
3.5.2, 4.4.3.1.1, 4.4.3.3.7, 4.4.3.5.7, 4.4.3.6.4, 4.4.3.9.49, 4.4.3.9.50, 5.4.3, 5.5.1,
7.6, 7.8, 7.13.2.
Updated Section: 3.2.1.2, 3.4.2.2.8, 3.4.2.3.2, 3.4.2.3.3, 3.4.2.5.2, 3.4.2.5.4, 3.4.3,
3.5.2.13, 3.5.3.2, 3.5.3.3.1.1, 3.5.3.3.1.3, 3.5.5.2, 3.5.5.3.1. 3.5.5.3.2, 3.5.6.1, 3.5.7,
4.4.3.1.6, 4.4.3.5.7, 4.4.3.6.13, 4.4.3.7.6, 4.4.3.9.5, 4.4.3.10.5, 4.4.3.10.6, 4.4.3.10.7,
4.4.3.10.8, 4.4.3.10.9, 4.4.3.13.8, 4.4.3.13.15, 4.4.3.13.23, 4.4.3.13.24, 4.4.3.13.25,
5.4.2, 5.5.1, 5.5.2, 5.6.6, and 5.6.6.1.
Updated Table 5-2, 5-6 and supported figure.
Updated Figure 5-1 notes.
Added Section 7.16.8.
Section 4.4.3.5.12, Drop Enable Control – DROPEN (0x03D04 – 0x03D08; RW)
-
Description updated for clarity.
Section 5.3.13, Sample Configurations
- Sample filtering configurations added.
Section 9.1.1, GHOST ECC Register - GHECCR (0x110B0, RW).
Diagnostic register added
to public documentation because it has limited public use as a workaround.
Support for PCIe* Statistics Counters dropped.
Section 3.4.2.2, PBA Number Module – Words 0x15:0x16.
Updated to reflect new
methodology.
2.4
August 2008
2.5
November
2008
3.1
April 2009
3.2
October 24,
2010
3.21
December 9,
2010
December 15,
2011
September
2012
Minor corrections.
3.22
Section 3.4.5.1.7.7, NC-SI Configuration (0ffset 0x06).
Updated.
3.23
Section 3.4.3.2.1, Analog Configuration Sections – Words 0x04:0x05.
Updated. In the
table, "configuration data" and "configuration addess" were swapped.
Section 3.4.3.2.1.2, EEPROM Analog Configuration – Data Word.
Section content
updated. Now reads “Each word in the analog configuration section has the same
structure: bits 7:0 are the register data and bits 15:8 are the registers address. The
analog registers are eight bits wide with an 8-bit address width. After reading the
EEPROM word, the register specified in bits 15:8 is loaded with the data from bits 7:0.”
3
Intel
®
82598EB 10 GbE Controller - Contents
Contents
1.
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
General Information
..................................................................................................................11
Introduction ................................................................................................................................ 11
Terminology and Acronyms ...........................................................................................................11
Reference Documents ...................................................................................................................14
Models and Symbols .....................................................................................................................15
Physical Layer Conformance Testing ...............................................................................................15
Design and Board Layout Checklists................................................................................................15
Number Conventions ....................................................................................................................16
System Configurations ..................................................................................................................16
External Interfaces .......................................................................................................................17
1.9.1
PCIe Interface ................................................................................................................18
1.9.2
XAUI Interfaces ..............................................................................................................18
1.9.3
EEPROM Interface ...........................................................................................................19
1.9.4
Serial Flash Interface.......................................................................................................20
1.9.5
SMBus Interface .............................................................................................................20
1.9.6
NC-SI Interface ..............................................................................................................20
1.9.7
MDIO Interfaces..............................................................................................................20
1.9.8
Software-Definable Pins (SDP) Interface (General-Purpose I/O).............................................21
1.9.9
LED Interface .................................................................................................................21
Signal Descriptions and Pinout List............................................................................................23
Signal Type Definitions .................................................................................................................23
PCIe Interface ............................................................................................................................. 24
XAUI Interface Signals ..................................................................................................................26
EEPROM and Serial Flash Interface Signals ......................................................................................27
SMBus and NC-SI Signals..............................................................................................................28
MDI/O Signals ............................................................................................................................. 29
Software-Definable Pins ................................................................................................................29
LED Signals ................................................................................................................................. 30
Miscellaneous Signals ...................................................................................................................30
Test Interface Signals ...................................................................................................................31
Power Supplies ............................................................................................................................ 31
Alphabetical Pinout/Signal Name ....................................................................................................33
Internal/External Pull-Up/Pull-Down Specifications............................................................................46
Pin Assignments (Ball Out) ............................................................................................................48
Functional Description...............................................................................................................53
Interconnects ..............................................................................................................................53
3.1.1
PCIe..............................................................................................................................53
3.1.1.1
Architecture, Transaction and Link Layer Properties ..............................................54
3.1.1.2
General Functionality .......................................................................................55
3.1.1.3
Host Interface .................................................................................................55
3.1.1.4
Transaction Layer ............................................................................................59
3.1.1.5
Messages .......................................................................................................62
3.1.1.6
Ordering Rules ................................................................................................63
3.1.1.7
Transaction Definition and Attributes ..................................................................64
3.1.1.8
Flow Control ...................................................................................................65
3.1.1.9
Error Forwarding .............................................................................................67
3.1.1.10 Link Layer ......................................................................................................67
3.1.1.11 PHY ...............................................................................................................68
3.1.1.12 Error Events and Error Reporting .......................................................................71
3.1.1.13 Performance Monitoring....................................................................................75
3.1.1.14 Configuration Registers ....................................................................................75
3.1.2
Manageability Interfaces (SMBus/NC-SI) .......................................................................... 109
3.1.2.1
SMBus Pass-Through Interface ........................................................................ 109
3.1.2.2
NC-SI .......................................................................................................... 110
2.
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
3.
3.1
4
Intel
®
82598EB 10 GbE Controller - Contents
3.2
3.3
3.4
3.5
Non-Volatile Memory (EEPROM/Flash) .............................................................................. 111
3.1.3.1
EEPROM ....................................................................................................... 111
3.1.3.2
Flash............................................................................................................ 114
3.1.4
Network Interface ......................................................................................................... 116
3.1.4.1
10 GbE Interface ........................................................................................... 116
3.1.4.2
GbE Interface................................................................................................ 117
3.1.4.3
Auto Negotiation and Link Setup Features ......................................................... 117
3.1.4.4
MDIO/MDC ................................................................................................... 118
3.1.4.5
Ethernet (Legacy) Flow Control........................................................................ 119
3.1.4.6
MAC Speed Change at Different Power Modes .................................................... 121
Initialization .............................................................................................................................. 122
3.2.1
Power Up ..................................................................................................................... 122
3.2.1.1
Power-Up Sequence ....................................................................................... 122
3.2.1.2
Power-Up Timing Diagram .............................................................................. 124
3.2.1.3
Reset Operation ............................................................................................ 126
3.2.2
Specific Function Enable/Disable ..................................................................................... 129
3.2.2.1
General ........................................................................................................ 129
3.2.2.2
Overview ...................................................................................................... 129
3.2.2.3
Event Flow for Enable/Disable Functions ........................................................... 130
3.2.2.4
Device Disable Overview................................................................................. 131
3.2.3
Software Initialization and Diagnostics ............................................................................. 132
3.2.3.1
Power Up State ............................................................................................. 132
3.2.3.2
Initialization Sequence ................................................................................... 132
Power Management and Delivery.................................................................................................. 136
3.3.1
Power Delivery ............................................................................................................. 136
3.3.1.1
82598 Power States ....................................................................................... 137
3.3.1.2
Auxiliary Power Usage .................................................................................... 137
3.3.1.3
Interconnects Power Management.................................................................... 138
3.3.1.4
Power States................................................................................................. 140
3.3.1.5
Timing of Power-State Transitions.................................................................... 143
3.3.2
Wake Up ...................................................................................................................... 149
3.3.2.1
Advanced Power Management Wake Up ............................................................ 149
3.3.2.2
ACPI Power Management Wakeup .................................................................... 150
3.3.2.3
Wake-Up Packets........................................................................................... 151
NVM Map (EEPROM) ................................................................................................................... 157
3.4.1
EEPROM General Map .................................................................................................... 157
3.4.2
EEPROM Software Section .............................................................................................. 159
3.4.2.1
Compatibility Fields – Words 0x10-0x14 ........................................................... 159
3.4.2.2
PBA Number Module – Words 0x15:0x16 .......................................................... 159
3.4.2.3
Software EEGEN Work Area............................................................................. 160
3.4.2.4
PXE Configuration Words – Word 0x30:3B......................................................... 161
3.4.2.5
EEPROM Checksum Calculation ........................................................................ 165
3.4.3
Hardware EEPROM Sections............................................................................................ 166
3.4.3.1
EEPROM Init Section ...................................................................................... 166
3.4.3.2
EEPROM Hardware Pointers ............................................................................. 168
3.4.3.3
EEPROM PCIe General Configuration Section ..................................................... 171
3.4.3.4
EEPROM PCIe Configuration Space 0/1 Sections................................................. 178
3.4.3.5
EEPROM Core 0/1 Section ............................................................................... 179
3.4.3.6
EEPROM MAC 0/1 Sections .............................................................................. 182
3.4.4
Hardware Section – Auto-Read ....................................................................................... 187
3.4.5
Manageability Control Sections........................................................................................ 188
3.4.5.1
Common Firmware Pointers ............................................................................ 189
Rx/Tx Functions ......................................................................................................................... 208
3.5.1
Device Data/Control Flows.............................................................................................. 208
3.5.1.1
Transmit Data Flow ........................................................................................ 208
3.5.1.2
Rx Data Flow ................................................................................................ 209
3.5.2
Receive Functionality ..................................................................................................... 211
3.5.2.1
Packet Filtering ............................................................................................. 214
3.5.2.2
Intel® 82598 10 GbE Controller System Manageability Interface application
noteReceive Data Storage ............................................................................... 218
3.1.3
5
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